5.3. Clocks
| Signal Name | Direction | Description |
|---|---|---|
| i_p<n>_clk_ref[2:0] | In | The input clock i_clk_ref is the reference clock for the high-speed serial clocks and the datapath parallel clocks. E-Tile: 3 reference clocks is used with i_clk_ref[2:0] as defined below: i_clk_ref[0] - 156.25 MHz i_clk_ref[1] - 184.32 MHz i_clk_ref[2] - 153.6 MHz F-tile: 2 reference clocks is used with i_clk_ref[1:0] defined as follows: i_clk_ref[0]- FGT refclk clock -156.25 MHz i_clk_ref[1] - FHT refclk clock -156.25 MHz The System PLL and Common PLL reference clock configuration is selected through F-Tile Reference and System PLL Clock Intel FPGA IP drives this clock.
By default, FGT Refclk #2 is used in i_clk_ref[0] and FHT Refclk #0 is used in i_clk_ref[1] is used as reference clock for System PLL/Common PLL with frequency configured to 156.25 MHz. |
| i_clk_sys | In | Clock the system PLL clock from your design to the subsystem. You can do this when instantiating the System PLL outside the subsystem IP by setting the subsystem parameter EN_SYS_PLL. The clock frequency must be 830.07 MHz. |
| i_p<n>_clk_tx | In | TX data path clock. This clock drives the active TX interface for the port. This clock must be sourced from o_p<n>_clk_pll unless Enable asynchronous adapter clocks is selected. |
| i_p<n>_clk_rx | In | RX data path clock. This clock drives the active TX interface for the port. This clock must be sourced from o_p<n>_clk_pll unless Enable asynchronous adapter clocks selected. |
| i_p<n>_clk_tx_tod | In | Clock associated with TX Time-of-Day (ToD) input. Basic Accuracy Mode: Connect to any clock with frequency below:
Advanced Accuracy Mode: The o_p<n>_clk_tx_div must drive this clock. The clock frequency varies based on the Ethernet variant:
For more information, refer to the PTP Timestamp Accuracy section in E-tile Hard IP User Guide section and PTP Timestamp Accuracy section in F-tile Hard IP User Guide. |
| i_p<n>_clk_rx_tod | In | Clock associated with RX Time-of-Day (ToD) input. Basic Accuracy Mode: Connect to any clock with frequency below.
Advanced Accuracy Mode: The o_p<n>_clk_rec_div must drive this clock. The clock frequency varies based on the Ethernet variant:
For more information, refer to the E-tile Hard IP User Guide, PTP Timestamp Accuracy section and F-tile Hard IP User Guide, PTP Timestamp Accuracy section. |
| i_p<n>_clk_ptp_sample | In | Sample clock for PTP measurement. This is an external clock provided to the design with frequency of 114.285714 MHz (with required period of 8.75 ns) with ± 100 ppm.
Note: Applicable only when you set the PTP Accuracy Mode parameter to Advanced Mode.
For more information, refer to the E-tile Hard IP User Guide, PTP Timestamp Accuracy section and F-tile Hard IP User Guide, PTP Timestamp Accuracy section. |
| o_p<n>_clk_pll | Out | Hard IP for Ethernet block clock. E-tile: Supports the following clock frequencies:
This clock is reliable only after o_tx_pll_locked is asserted. F-tile: System PLL clock Clock derived from the F-Tile System PLL associated with the Ethernet IP port. The o_p<n>clk_pll frequency is equal to PLL frequency divided by 2. The following shows the o_p<n>clk_pll frequency unless you enabled custom system PLL frequency. Supports the following frequencies: 415.0390625 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), with Ethernet Technology Consortium RS(272, 258). The system PLL must be of 830.078125 MHz frequency or higher. |
| o_p<n>_clk_tx_div | Out | Hard IP for Ethernet block clock times 64/66. E-tile: Supports the following clock frequencies:
This clock is reliable only after o_tx_pll_locked is asserted. F-tile: Supports the following frequencies:
Clock recovered from the TX SERDES rate divided by either 33/66/68, depending on the FEC mode and Ethernet mode parameters. The o_clk_tx_div is equal to:
|
| o_p<n>_clk_rec_div64 | Out | Derived from RX recovered clock. This clock supports the SyncE standard. E-tile: The RX recovered clock frequency is:
This clock is reliable only after o_cdr_lock[n] is asserted. When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver reference clock with a filtered and divided version of o_p<n>_clk_rec_div64 or o_p<n>_clk_rec_div, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board.The IP core does not provide filtering.
Note: The RX recovered clock is not available for PTP PORT when PTP enabled.
F-tile: Supports the following frequencies:
Clock derived from RX recovered clock, divided by 64. |
| o_p<n>_clk_rec_div | Out | Derived from RX recovered clock. This clock supports the Synchronous Ethernet standard. E-tile: The RX recovered clock frequency is:
This clock is reliable only after o_cdr_lock[n] is asserted. When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of o_clk_rec_div64 or o_clk_rec_div, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering.
Note: The RX recovered clock is not available for PTP PORT when PTP enabled.
F-tile: Supports the following frequencies:
Clock derived from the RX recovered clock divided by either 33/66/68, depending on the FEC mode parameter. The o_clk_rec_div is equal to:
|
| o_p<n>_cdr_divclk | Out | For F-tile, clock output port typically used for SyncE applications. Only available for ports 8 through 15. To determine the frequency of this output, use the methodology specified in section 5.5 (Clock Connections in Synchronous Ethernet Operation) in the F-tile Ethernet Hard IP User Guide. |
| o_ehip<n/2>_ptp_clk_pll | Out | For E-tile, PLL clock outputs from PTP channels. There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels within the EHIP core. Supports the following clock frequencies:
|
| o_ehip<n/2>_ptp_clk_tx_div | Out | For E-tile, PLL clock outputs from PTP channels. There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels within the EHIP core. Hard IP for Ethernet block clock times 64/66. Supports the following clock frequencies:
This clock is reliable only after o_tx_pll_locked is asserted. |
| o_ehip<n/2>_ptp_clk_rec_div64 | Out | For E-tile, these are PLL clock outputs from PTP channels. There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels with in the EHIP core. Derived from RX recovered clock. This clock supports the SyncE standard. The RX recovered clock frequency is:
When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver reference clock with a filtered and divided version of o_clk_rec_div64 or o_clk_rec_div66, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering.
Note: The RX recovered clock is not available for PTP PORT when PTP enabled.
|
| o _ehip<n/2>_clk_rec_div | Out | For E-tile, these are PLL clock outputs from PTP channels. There are 2 PTP channels for each enabled EHIP Core. These clocks are available only if PTP is enabled in any one of the channels with in the EHIP core. Derived from RX recovered clock. This clock supports the SyncE standard. The RX recovered clock frequency is:
This clock is reliable only after o_cdr_lock[n] is asserted. When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of o_clk_rec_div64 or o_clk_rec_div66, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering.
Note: The RX recovered clock is not available for PTP PORT when PTP enabled.
|
| i_p<n>_async_clk_tx | In | For E-tile, this clock drives the TX interface for 25GbE profile when Asynchronous mode is enabled. The clock frequency must be within 390.625 MHz and 402.83203125 MHz. |
| i_p<n>_async_clk_rx | In | For E-tile, this clock drives the RX interface for 25GbE profile when Asynchronous mode is enabled. The clock frequency must be within 390.625 MHz and 402.83203125 MHz. |