Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping 3.4. Analog Parameter Options
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Asynchronous Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status 7.1.21. HSSI Hotplug Debug Port Control 7.1.22. HSSI Hotplug Debug Port Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

4.3.1.6. read_MAC_statistic

Table 28.   read_MAC_statistic The following table above shows the statistic counters of Ethernet Subsystem and the mapping to internal Ethernet IP statistic registers. You write to HSSI Control/Address CSR to specify which counter should be read from this table. The Ethernet subsystem computes these counter values by aggregating internal MAC statistic register values retrieved from the Ethernet IP. The HSSI Control/Address bit 31 indicates whether the read is intended for the LSB 32 bits (1'b1) or the MSB 32 bits (1'b0) of the statistic counters.
Ethtool Statistics HSSI Control/Address bit[20:16] Counters Other Ethernet MAC Counters(F-Tile) E-tile Hard IP for Ethernet Statistics Registers
tx_packets 0 cntr_tx_mcast_data_ok + cntr_tx_bcast_data_ok +cntr_tx_ucast_data_ok +cntr_tx_mcast_ctrl_ok +cntr_tx_bcast_ctrl_ok +cntr_tx_ucast_data_ok TX_MCAST_DATA_OK_31_0 + TX_MCAST_DATA_OK_63_32+ TX_BCAST_DATA_OK_31_0 + TX_BCAST_DATA_OK_63_32 + TX_UCAST_DATA_OK_31_0 + TX_UCAST_DATA_OK_63_32 + TX_MCAST_CTRL_OK_31_0 + TX_MCAST_CTRL_OK_63_32 + TX_BCAST_CTRL_OK_31_0 + TX_BCAST_CTRL_OK_63_32 + TX_UCAST_CTRL_OK_31_0 + TX_UCAST_CTRL_OK_63_32
rx_packets 1 cntr_rx_mcast_data_ok + cntr_rx_bcast_data_ok +cntr_rx_ucast_data_ok +cntr_rx_mcast_ctrl_ok +cntr_rx_bcast_ctrl_ok +cntr_rx_ucast_data_ok RX_MCAST_DATA_OK_31_0 + RX_MCAST_DATA_OK_63_32+ RX_BCAST_DATA_OK_31_0 + RX_BCAST_DATA_OK_63_32 + RX_UCAST_DATA_OK_31_0 + RX_UCAST_DATA_OK_63_32 + RX_MCAST_CTRL_OK_31_0 + RX_MCAST_CTRL_OK_63_32 + RX_BCAST_CTRL_OK_31_0 + RX_BCAST_CTRL_OK_63_32 + RX_UCAST_CTRL_OK_31_0 + RX_UCAST_CTRL_OK_63_32
rx_crc_errors 2 cntr_rx_fcs RX_FCSERR_31_0+ RX_FCSERR_63_32
rx_align_errors 3 cntr_rx_fcs - cntr_rx_runt RX_FCSERR_31_0+ RX_FCSERR_63_32 - (RX_RNT_31_0 + RX_RNT_63_32)
tx_bytes 4 cntr_tx_payloadoctetsok TX_Payload_OctetsOK_31_0+ TX_Payload_OctetsOK_63_32
rx_bytes 5 cntr_rx_payloadoctetsok RX_Payload_OctetsOK_31_0+ RX_Payload_OctetsOK_63_32
tx_pause 6 cntr_tx_pause TX_PAUSE_31_0+ TX_PAUSE_63_32
rx_pause 7 cntr_rx_pause RX_PAUSE_31_0+ RX_PAUSE_63_32
rx_errors 8 cntr_rx_dropped RX_Dropped_CTRL_31_0+ RX_Dropped_CTRL_63_32
tx_errors 9 cntr_tx_dropped TX_Dropped_CTRL_31_0+ TX_Dropped_CTRL_63_32
rx_unicast 10 ctnr_rx_ucast_data_ok +cntr_rx_ucast_ctrl_o RX_UCAST_DATA_OK_31_0 + RX_UCAST_DATA_OK_63_32+ RX_UCAST_CTRL_OK_31_0 + RX_UCAST_CTRL_OK_63_32
rx_multicast 11 ctnr_rx_mcast_data_ok +cntr_rx_mcast_ctrl_ok RX_MCAST_DATA_OK_31_0 + RX_MCAST_DATA_OK_63_32+ RX_MCAST_CTRL_OK_31_0 + RX_MCAST_CTRL_OK_63_32
rx_broadcast 12 ctnr_rx_bcast_data_ok +cntr_rx_bcast_ctrl_ok RX_BCAST_DATA_OK_31_0 + RX_BCAST_DATA_OK_63_32+ RX_BCAST_CTRL_OK_31_0 + RX_BCAST_CTRL_OK_63_32
tx_discards 13 0 -
tx_unicast 14 ctnr_tx_ucast_data_ok +cntr_tx_ucast_ctrl_ok TX_UCAST_DATA_OK_31_0 + TX_UCAST_DATA_OK_63_32+ TX_UCAST_CTRL_OK_31_0 + TX_UCAST_CTRL_OK_63_32
tx_multicast 15 ctnr_tx_mcast_data_ok +cntr_tx_mcast_ctrl_ok TX_MCAST_DATA_OK_31_0 + TX_MCAST_DATA_OK_63_32+ TX_MCAST_CTRL_OK_31_0 + TX_MCAST_CTRL_OK_63_32
tx_broadcast 16 ctnr_tx_bcast_data_ok +cntr_tx_bcast_ctrl_ok TX_BCAST_DATA_OK_31_0 + TX_BCAST_DATA_OK_63_32+ TX_BCAST_CTRL_OK_31_0 + TX_BCAST_CTRL_OK_63_32
ether_drops 17 cntr_rx_dropped RX_Dropped_CTRL_31_0+ RX_Dropped_CTRL_63_32
rx_total_bytes 18 rxoctetsok RX_Frame_OctetsOK_31_0+ RX_Frame_OctetsOK_63_32
rx_total_packets 19 cntr_rx_mcast_data_ok + cntr_rx_bcast_data_ok +cntr_rx_ucast_data_ok +cntr_rx_mcast_ctrl_ok +cntr_rx_bcast_ctrl_ok +cntr_rx_ucast_data_ok +cntr_rx_mcast_data_err + cntr_rx_bcast_data_err +cntr_rx_ucast_data_err +cntr_rx_mcast_ctrl_err+cntr_rx_bcast_ctrl_err +cntr_rx_ucast_data_err TX_MCAST_DATA_OK_31_0 + TX_MCAST_DATA_OK_63_32 + TX_BCAST_DATA_OK_31_0 + TX_BCAST_DATA_OK_63_32 + TX_UCAST_DATA_OK_31_0 + TX_UCAST_DATA_OK_63_32 + TX_MCAST_CTRL_OK_31_0 + TX_MCAST_CTRL_OK_63_32 + TX_BCAST_CTRL_OK_31_0 + TX_BCAST_CTRL_OK_63_32 + TX_UCAST_CTRL_OK_31_0 + TX_UCAST_CTRL_OK_63_32 + RX_MCAST_DATA_ERR_31_0 + RX_MCAST_DATA_ERR_63_32+ RX_BCAST_DATA_ERR_31_0 + RX_BCAST_DATA_ERR_63_32 + RX_UCAST_DATA_ERR_31_0 + RX_UCAST_DATA_ERR_63_32 + RX_MCAST_CTRL_ERR_31_0 + RX_MCAST_CTRL_ERR_63_32 + RX_BCAST_CTRL_ERR_31_0 + RX_BCAST_CTRL_ERR_63_32 + RX_UCAST_CTRL_ERR_31_0 + RX_UCAST_CTRL_ERR_63_32
rx_undersize 20 cntr_rx_runt RX_RNT_31_0+ RX_RNT_63_32
rx_oversize 21 cntr_rx_oversize RX_OVERSIZE_31_0+ RX_OVERSIZE_63_32
rx_64_bytes 22 cntr_rx_64b RX_64B_31_0+ RX_64B_63_32
rx_65_127_bytes 23 cntr_rx_65to127b RX_65to127B_31_0+ RX_65to127B_63_32
rx_128_255_bytes 24 cntr_rx_128to255b RX_128to255B_31_0+ RX_128to255B_63_32
rx_256_511_bytes 25 cntr_rx_256to511b RX_256to511B_31_0+ RX_256to511B_63_32
rx_512_1023_bytes 26 cntr_rx_512to1023b RX_512to1023B_31_0+ RX_512to1023B_63_32
rx_1024_1518_bytes 27 cntr_rx_1024to1518b RX_1024to1518B_31_0+ RX_1024to1518B_63_32
rx_gte_1519_bytes 28 cntr_rx_1519tomax RX_1519toMAXB_31_0+ RX_1519toMAXB_63_32
rx_jabbers 29 cntr_rx_jabbers RX_JABBERS_31_0+ RX_JABBERS_63_32
rx_runts 30 cntr_rx_fragments RX_ FRAGMENTS _31_0+ RX_ FRAGMENTS _63_32
Level Two Title