Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 10/02/2023
Public

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1.4. Resource Utilization

The following tables present preliminary resource utilization of the Ethernet Subsystem IP across Ethernet rates, IP Core variations, and tiles.
Table 5.  Ethernet Subsystem Intel FPGA IP Resource Utilization for E-Tile
Ethernet Configuration IP Core Version Logic Utilization (in ALMs) Dedicated Logic Registers M20K RAM Blocks
16x10GE-1 PTP(without TX Packet Classifier) 66,665 145,814 325
8x25GE-1 RSFEC + PTP 34,421 74,285 229
4x100GE-4 RSFEC + PTP 58,349 110,733 281
Table 6.  Ethernet Subsystem Intel FPGA IP Resource Utilization for F-Tile
Ethernet Configuration IP Core Version Logic Utilization (in ALMs) M20K RAM Blocks
1x400GE-8 With FEC, PTP 40914.3 301
1610GE-1 ANLT 63994.2 296
16x25GE-1 ANLT 64469.0 296
4x100GE-4 ANLT 32810.5 244
16x10GE-1 ANLT 55,885 536
16x25GE-1 ANLT 66,925 627
4x100GE-4 ANLT 75,725 687