Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.4. Resets

Table 42.  Reset Signals
Signal Name Direction Type Description
subsystem_cold_rst_n In Reset

Asynchronous, active-low hard global reset.

Resets the TX MAC, RX MAC, TX PCS, RX PCS, transceivers (transceiver reconfiguration registers and interface), and Ethernet reconfiguration registers.

This reset leads to the de-assertion of the o_tx_lanes_stableand o_rx_pcs_ready output signals.

i_p<n>_tx_rst_n In Reset

Asynchronous, active-low hard reset.

Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the de-assertion of the o_tx_lanes_stable output signal.

i_p<n>_rx_rst_n In Reset

Asynchronous, active-low hard reset.

Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the de-assertion of the o_rx_pcs_ready output signal.

o_p<n>_tx_rst_ack_n Out Reset Acknowledge

Activelow acknowledge signal for i_tx_rst_n.

The user should not de-assert i_tx_rst_n until o_tx_rst_ack_n is asserted.

o_p<n>_rx_rst_ack_n Out Reset Acknowledge

Activelow acknowledge signal for i_rx_rst_n.

The user should not de-assert i_rx_rst_n until o_rx_rst_ack_n is asserted.

subsystem_cold_rst_ack_n Out Reset Acknowledge

Activelow acknowledge signal for subsystem_cold_rst_n.

The user should not de-assert subsystem_cold_rst_n until subsystem_cold_rst_ack_nis asserted.