Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 10/02/2023
Public

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5.1.3. AXI-ST PHY Direct

The AXI-ST PHY Direct Interface is available when user select below profiles as Subsystem Profiles for specific port.

Ethernet PMA/FEC/PCS-Direct, MII, General PMA/FEC/PCS-Direct, OTN, Flex-E, TSE PCS

Please refer to AXI-ST Client Interface section for detail on the existence of AXI-ST PHY Direct and AXI-ST Client interface when DR Extension Subsystem is enabled.

Table 31.  Tx PHY Direct Functional Signals
Signal Name Direction Type Description
p{0..NUM_PORT}_app_ss_st_txphydirect_clk In Clock The TX clock for the IP core that drives the channel.
p{0..NUM_PORT}_app_ss_st_ txphydirect_areset_n[PORTX_CHANNEL-1:0] In Reset Asynchronous reset.
p{0..NUM_PORT}_app_ss_st_ txphydirect_tdata[PORTX_CHANNEL-1:0][ PORTX_DATA_WIDTH-1:0] In Data Tx PHY Direct parallel data
p{0..NUM_PORT}_ss_app_st_ txphydirect_tready [PORTX_CHANNEL-1:0] Out Status Ready signal for PHY Direct data
p{0..NUM_PORT}_app_ss_st_ txphydirect_tvalid [PORTX_CHANNEL-1:0] In Status Valid signal for PHY Direct data
Table 32.  Rx PHY Direct Functional Signals
Signal Name Direction Type Description
p{0..NUM_PORT}_app_ss_st_rxphydirect _clk In Clock

The RX clock for the IP core that drives the channel.

p{0..NUM_PORT}_app_ss_st_ rxphydirect_areset_n[PORTX_CHANNEL-1:0] In Reset Asynchronous reset.
p{0..NUM_PORT}_ss_app_st_ rxphydirect_tdata[PORTX_CHANNEL-1:0][PORTX_DATA_WIDTH-1:0] Out Data Rx PHY Direct parallel data.
p{0..NUM_PORT}_ss_app_st_ rxphydirect_tvalid Out Status Valid signal for PHY Direct data.