Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

3.1. Parameter Editor Parameters

The Ethernet Subsystem Intel FPGA IP parameter has two tabs, Ethernet Subsystem tab and an Example Design tab.

For more information about the Example Design tab, refer to Ethernet SS IP Example Design.

Table 9.  Ethernet Subsystem Intel FPGA IP Parameters: HSSI<n> is the enabled port number, ranging from 0 to 15
Parameter Range Default Setting Parameter Description
Number of devices 1 1 Only 1 device is supported in this version.
Device 0 Configuration
Tile 0 Configuration
Tiles E, F E Per tile configuration which shows the supported tiles within the subsystem. The allowed values are based on the FPGA device.
Main Configuration
General Configuration
Product Agilex Agilex Only Agilex is supported in this version.
NUM_ENABLED_PORTS 1-16 1

Set the number of

10GE/25GE/40GE/50GE/100GE/200GE/400GE port(s) to be enabled. The IP will determine the number of transceiver channels based on the port profile.

Enable JTAG to Avalon® Master Bridge
  • Enable
  • Disable
Disable

Enable this parameter to add a JTAG to Avalon® memory-mapped interface Master bridge connecting internally to reconfiguration registers. This allows the Ethernet Toolkit to be run using System Console.

Note that Ethernet Toolkit is not available for multi-port ANLT designs with this Quartus release.

Enable ECC Protection
  • Enable
  • Disable
Disable Enables ECC protection. Enabling this option can improve data integrity in memory blocks.
Port_<port_number:1-16>Port_<n>_configuration
Note: Depending on selected port profile, there will be up to 16 ports that can be individually configured.
PORT<n>_ENABLE
  • 0
  • 1
1 Set this parameter to 1 to enable individual port.
Port_PORT<n>_PROFILE
  • 10GbE (E- and F-tile)
  • 25GbE (E- and F-tile)
  • 40GCAUI-4(F-tile only)
  • 50GAUI-1 (F-tile only)
  • 50GAUI-2 (F-tile only)
  • 100GAUI-1 (F-tile only)
  • 100GCAUI-4 (E- and F-tile)
  • 100GCAUI-2 (E- and F- tile)
  • 200GAUI-4 (F-tile only)
  • 200GAUI-2 (F-tile only)
  • 200GAUI-8 (F-tile only)
  • 400GAUI-8 (F-tile only)
  • 400GAUI-4 (F-tile only)
  • CPRI (E-Tile only)
 10GbE Select the speed rate profile for each port. For E-tile, 100G CAUI-4 variant can only be selected on ports 0,4,8,12.
PORT<n>_SUB_PROFILE
  • MAC+PCS (E- and F-Tile)
  • PCS (E-Tile)
  • OTN (E-Tile)
  • FlexE (E-Tile)
 MAC+ PCS Select the Ethernet Protocol layer sub-profile for the port.
PORT<n>_RSFEC
  • True
  • False
False

Set this parameter to True to include additional hard logic to perform

Reed-Solomon Forward Error Correction (RS-FEC). This feature is not supported for 10GbE profile.

PORT<n>_PTP
  • True
  • False
False Set this parameter to True to add IEEE 1588 PTP Timestamp offload functions to the core. The core can generate 1-step or 2-step TX timestamps and RX timestamps.
Dynamic Reconfiguration
  • Enable
  • Disable
Disable Enables Dynamic reconfiguration for port. Only available for selected profiles:
  • 25G Ethernet+RS-FEC
  • 25G Ethernet Protocol+PTP+RS-FEC
  • 24G CPRI + RS-FEC
  • 1x100G MAC + PCS +RS-FEC
Note: This paramter is only applicable for E-Tile.
100G Partial Reconfiguration DR Extension Subsystem
  • Enable
  • Disable
Disable

This parameter is only applicable for E-Tile.

Enables Dynamic Reconfiguration Subsystem with Partial Reconfiguration support where the same 100G interface ports are used for the 25G profile as well. Supported only for E-tile DR base profile: 1x100G MAC + PCS+ RSFEC.

Table 10.  E-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab
Parameter Range Default Setting Parameter Description
IP Configuration
Note: Each enabled port will have individual port configuration tab
P<n> IP P<n> PMA_Adaptation
Port <n> Configuration
P<n> General Options
ENABLE AN/LT
  • On
  • Off
 Off Turn on this parameter to enable the IP core to support Auto-negotiation and Link Training (AN/LT).
Enable Native PHY Debug Master Endpoint
  • On
  • Off
 On

If this parameter is turned on, the underlying Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint that connects internally to the Avalon memory-mapped slave interface for dynamic reconfiguration. The Native PHY Debug Master Endpoint can access the reconfiguration registers of the transceiver.

This connection allows the System Console to run the Transceiver Toolkit.

Note that Transceiver Toolkit is not available for multi-port ANLT designs with this Quartus release.
ENABLE SYNCE
  • On
  • Off
 Off Turn on this parameter to enable the IP core to support SyncE operation.
P<n> PTP Options
Note: Only available when PTP is enabled for the port.

Enable Tx PTP Packet

Classifier

  • True
  • False
False Set this parameter to True to include PTP Packet Classifier in transmit direction, where PTP sideband signals will be generated based on PTP packet decoding.
PTP Accuracy Mode
  • Basic Mode
  • Advanced Mode
Basic Mode

When selected, specifies the PTP timestamp accuracy for selected Ethernet variant.

For 10GbE/25GbE variant:

  • Basic Mode: PTP accuracy is ± 3 ns
  • Advanced Mode: PTP accuracy is ±1.5 ns
For 100GbE variant:
  • Basic Mode: PTP accuracy is ± 8 ns
  • Advanced Mode: not supported
P<n> AN/LT Options
P<n> Auto-Negotiation (AN)
Note: Only available when AN/LT is enabled for the port.
Enable Auto-Negotiation on reset
  • On
  • Off
On

If this parameter is turned on, the IP core is configured after reset to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3–2015.

If this parameter is turned off, the IP core does not perform the auto-negotiation after reset.

Link Fail Inhibit Time 100-4000ms 504ms Specify the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK.
Advertise CR Technology Ability
  • On
  • Off
 On

If this parameter is turned on, the IP core advertises CR capability by default.

If this parameter is turned off, the IP core advertises KR capability by default.

Request RSFEC
  • On
  • Off
 On Turn on this parameter to request RSFEC from remote link partner during auto-negotiation.
Auto-Negotiation Master
  • Lane 0
  • Lane 1
  • Lane 2
  • Lane 3
PLane 0 Select the master channel for auto-negotiation. Available for 100GbE variant.
Advertise both 10G and 25G during AN
  • On
  • Off
 Off

Turn on this parameter to advertise both 10 and 25 Gbps data rate during auto-negotiation. When this parameter is turned off, the IP core advertises only the data rate specified in port profile.

This parameter is not available for 100GbE variant.

Advertise PAUSE ability
  • On
  • Off
 On

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.

Advertise PAUSE ASM_DIR ability
  • On
  • Off
 On

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.

P<n> Link Training
Note: Only available when AN/LT is enabled for the port.
Enable Link Training on reset
  • On
  • Off
 On If this parameter is turned on, the IP core is configured after reset to perform link training, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER).
Enable Link Training for VSR recipe
  • On
  • Off
 Off If this parameter is turned on, the IP core will use the VSR recipe during Link Training. Use during internal loopback or with very short connections.
P<n> PMA Options Configuration
Enable HOTPLUG
  • On
  • Off
 Off If this parameter is turned on, the IP core will enable autonomous logic to detect a valid signal on the serial interface and tune the link.

The hotplug module supports 10GE, 25GE, and 100GE NRZ rates for LR and VSR recipes. If PAM4 is enabled, the module will always load the VSR recipe. If you are not using your own adaptation recipe for PAM4 designs, Intel recommends enabling the Hotplug module.

For ANLT-enabled channels, the Hotplug module will start after the ANLT engine enters "Data Mode". The hotplug module will overwrite the recipe of the ANLT module with either the VSR or LR recipe. If ANLT fails, the hotplug module will never start.

Hotplug is not supported for CPRI rates.
Enable iCAL and pCAL recipe at power on.
  • On
  • Off
 Off Available when AN/LT is disabled on NRZ ports. Not available on PAM4 ports. If this parameter is turned on, the IP core will load PMA Configuration 0 prior to running initial calibration. Continuous calibration will run on every power-on or IP cold reset.
Enable custom rate
  • On
  • Off
 Off If this parameter is turned on, the IP core will enable the Custom Rate Interface.
Include deterministic latency measurement interface
  • On
  • Off
 Off If this parameter is turned on, the IP core will enable the Deterministic Latency Interface.
PHY Reference Frequency (MHz) 156.25MHz 156.25MHz Select the expected transceiver reference clock frequency.
P<n>Configuration Tab
P<n>MAC Options Configuration
P<n>Basic Configuration
TX Maximum Frame Size 65-65535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.
RX Maximum Frame Size 65-65535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the RX statistics counters.
Enforce Maximum Frame Size
  • On
  • Off
 Off Specify whether the IP core can receive an oversized packet or truncates these packets.
Choose Link Fault Generation Mode
  • OFF
  • Unidirectional
  • Bidirectional
 Bidirectional

Specify the IP core response to link fault events.

Bidirectional link fault handling complies with the Ethernet specification. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility.

Stop TX Traffic when link partner sends PAUSE
  • Yes
  • No
  • Disable Flow Control
No

Select how the IP core responds to PAUSE frames from the Ethernet link.

This parameter has no effect if flow control is disabled. If you disable flow control, the IP core neither responds to incoming PAUSE and PFC frames nor generates outgoing PAUSE and PFC frames.

If this parameter has the value of No, you can use the i_tx_pause signal on the TX client interface to force the TX MAC to stop TX traffic.

Bytes to remove from RX frames
  • None
  • Remove CRC bytes
  • Remove CRC and PAD bytes
 Remove CRC bytes

Select bytes from incoming RX frames to be removed by the RX MAC before passing the bytes to the RX MAC Client.

If the PAD and CRC bytes are not needed downstream, the remove option can reduce the need for downstream packet processing logic.

Forward RX Pause Requests
  • On
  • Off
 Off

Select whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface or drops them after internal processing.

Note: This parameter has no effect if flow control is disabled.
Use Source Address Insertion
  • On
  • Off
 Off

If the parameter is turned on, the IP core overwrites the outgoing packet source address with the value from TXMAC_SADDR registers.

If the parameter is turned off, the IP core does not overwrite the source address.
Enable TX VLAN Detection
  • On
  • Off
 On

If the parameter is turned on, the IP core identifies VLAN or Stacked VLAN frames in TX statistics as VLAN or SVLAN frames.

If the parameter is turned off, the IP core treats these frames as regular control frames.
Enable RX VLAN Detection
  • On
  • Off
 On

If the parameter is turned on, the IP core identifies VLAN or Stacked VLAN frames in RX statistics as VLAN or SVLAN frames.

If the parameter is turned off, the IP core treats these frames as regular control frames.
P<n>Specialized Configuration
Enable Preamble Passthrough
  • On
  • Off
 Off If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.
Enable strict preamble check
  • On
  • Off
 Off If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).
Enable strict SFD check
  • On
  • Off
 Off If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).
Average Inter-packet gap
  • 1
  • 8
  • 10
  • 12
 12

Specifies the average minimum inter-packetgap (IPG) the IP core maintains on the TX Ethernet link.

The default value of 12 complies with the Ethernet standard.

The remaining values support increased throughput.
Additional IPG removed as per AM period Integer 0 Specifies the number of inter- packets gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance.

For parameters in the Ethernet Subsystem – IP Configuration tab, refer to the PMA Adaptation topic in the E-Tile Transceiver PHY User Guide.

Table 11.  F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab
Parameter Range Default Setting Parameter Description
F-Tile IP Configuration
Note: Each enabled port will have individual port configuration tab
Port<n>configuration
P <n> IP
P <n> General Options
Client Interface
  • MAC segmented
  • MAC Avalon ST
 MAC segmented Selects which Ethernet internal protocol layers are provided to the client interface
FEC Mode
  • IEEE 802.3 BASE-R Firecode (CL 76)
  • IEEE 802.3 RS(528,514) (CL 91)
  • IEEE 802.3 RS(544,514) (CL 134)
  • Ethernet Technology Consortium RS (272,258)
 IEEE 802.3 RS(528,514) (CL 91) When FEC is enabled in the Main Configuration tab, this option selects which FEC mode the port will use
Enable debug endpoint for transceiver toolkit
  • Enable
  • Disable
 Disable When enabled, an embedded Native Phy Debug Endpoint connects internally to the AVMM slave interface for the use of transceiver toolkit.
Enable asynchronous adapter clocks Disable Disable Allows you to drive p<n>_app_ss_st_rx_clk and p<n>_app_ss_st_tx_clk from different sources.
Enable dedicated CDR clock output
  • Enable
  • Disable
 Disable Enables CDR clock output. When channel number is more than one, the CDR clock output is connected to channel 0 of the port. This option is only applicable if Channel 0 is within FGT Quad3 or FGT Quad2 (i.e ports 8 o2 12)
Include 40GE
  • Enable
  • Disable
 Disable Used with Dynamic Reconfiguration. When enabled, 40GE is supported for FGT PMAs with the 100GE-4 Reconfiguration Group with the MAC segmented Client Interface.
Include 32bit soft CWBIN counters
  • Enable
  • Disable
 Disable When enabled, the port includes 32bit soft counters for RSFEC corrected cwbin counters.
Port<n> DR configuration
Note: Only enabled when Dynamic Reconfiguration is selected per port. Refer to the F-tile Ethernet Multirate Intel FPGA IP User Guide for further information on the Dynamic Reconfiguration parameters.
Number of Secondary profiles 1 through 32 1 Selects the number of secondary profiles for this DR port
P<n> Startup Profile Options
Startup profile
  • 1x100GE-4
  • 1x100GE-2
  • 2x50GE-2
  • 2x50GE-1
  • 4x25GE-1/10GE-1
 Per Base Profile

Selects the startup profile for each Reconfigurable Group
Startup profile- Port<3:0> Profile-0 (Base Profile) to Profile-<number of secondary profiles in Reconfigurable Group> Per Base Profile Selects the startup profile for Port
P<n> Base_Profile(Profile #0)
Note: MAC Option parameters on this tab are described in P<n> Basic and P<n> Specialized sections
Ethernet Mode Base Profile Base Profile —
P<n> Profile [Number of Profiles per port]
Note: MAC Option parameters on this tab are described in P<n> Basic and P<n> Specialized sections
Ethernet Mode 400G-4 - 4x10GE-1 Base Profile Selects Ethernet mode for this profile
FEC mode None - IEEE 802.3 RS(544,514) (CL134) None

Selects the FEC mode for this profile
Associated Port Number Port 0 - ALL Port 0

Select the associated port number. When ALL is selected, this is equivalent to all ports of the Reconfigurable Group being used.

MAC settings same as Profile 0
  • Enable
  • Disable
 Disable When enabled, the MAC settings from Profile0 are copied to current profile
Enable FHT pre-encoder
  • Enable
  • Disable
 Disable When enabled, the Pre-encoder for the FHT PMA is enabled.
P<n> PTP Options
Note: Only available when PTP is enabled for the port.
Enable Tx PTP Classifier false, true false Set this parameter to True to include PTP Packet Classifier in transmit direction, where PTP sideband signals will be generated based on PTP packet decoding.
Timestamp accuracy mode Basic, Advanced Basic

When selected, specifies the PTP timestamp accuracy for selected Ethernet variant.

For 10GbE/25GbE/50GbE variant:
  • Basic Mode: PTP accuracy is ± 3 ns
  • Advanced Mode: PTP accuracy is ±1.5 ns
For 100GbE/200GbE/400GbE variant:
  • Basic Mode: PTP accuracy is ± 8 ns
  • Advanced Mode: not supported

Not applicable for 40GbE variant
Timestamp fingerprint width 8-32 8 Defines the timestamp fingerprint bit width
P<n> Auto-Negotiation and Link Training Options
P<n> ANLT Options
Note: Only available when AN/LT is enabled for the port
Enable Link Training on reset
  • On
  • Off
 On If this parameter is turned on, the IP core is configured after reset to perform link training, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER).
Enable Auto-Negotiation on reset
  • On
  • Off
On

If this parameter is turned on, the IP core is configured after reset to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3–2015.

If this parameter is turned off, the IP core does not perform the auto-negotiation after reset.

KR or CR mode
  • CR mode
  • KR mode
 CR mode Selects KR or CR mode for ANLT
Link Fail Inhibit Time 100-4000ms 504ms Specify the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK.
AN channel location 0 0-7 0 Auto negotiation lane for port
P<n>MAC Options
P<n>Basic
TX Maximum Frame Size 65-65535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.
RX Maximum Frame Size 65-65535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the RX statistics counters.
Enforce Maximum Frame Size
  • On
  • Off
 Off Specify whether the IP core can receive an oversized packet or truncates these packets.
Link Fault Generation Mode
  • OFF
  • Unidirectional
  • Bidirectional
 Bidirectional

Specify the IP core response to link fault events.

Bidirectional link fault handling complies with the Ethernet specification. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility.

Stop TX Traffic when link partner sends PAUSE
  • Yes
  • No
  • Disable Flow Control
No

Select how the IP core responds to PAUSE frames from the Ethernet link.

This parameter has no effect if flow control is disabled. If you disable flow control, the IP core neither responds to incoming PAUSE and PFC frames nor generates outgoing PAUSE and PFC frames.

If this parameter has the value of No, you can use the i_tx_pause signal on the TX client interface to force the TX MAC to stop TX traffic.

Bytes to remove from RX frames
  • None
  • Remove CRC bytes
  • Remove CRC and PAD bytes
 Remove CRC bytes

Select bytes from incoming RX frames to be removed by the RX MAC before passing the bytes to the RX MAC Client.

If the PAD and CRC bytes are not needed downstream, the remove option can reduce the need for downstream packet processing logic.

Forward RX Pause Requests
  • On
  • Off
 Off

Select whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface or drops them after internal processing.

Note: This parameter has no effect if flow control is disabled.
Use Source Address Insertion
  • On
  • Off
 Off

If the parameter is turned on, the IP core overwrites the outgoing packet source address with the value from TXMAC_SADDR registers.

If the parameter is turned off, the IP core does not overwrite the source address.
Enable TX VLAN Detection
  • On
  • Off
 On

If the parameter is turned on, the IP core identifies VLAN or Stacked VLAN frames in TX statistics as VLAN or SVLAN frames.

If the parameter is turned off, the IP core treats these frames as regular control frames.
Enable RX VLAN Detection
  • On
  • Off
 On

If the parameter is turned on, the IP core identifies VLAN or Stacked VLAN frames in RX statistics as VLAN or SVLAN frames.

If the parameter is turned off, the IP core treats these frames as regular control frames.
P<n>Specialized Configuration
Enable Preamble Passthrough
  • On
  • Off
 Off If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass- through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.
Enable strict preamble check
  • On
  • Off
 Off If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).
Enable strict SFD check
  • On
  • Off
 Off If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).
Average Inter-packet gap
  • 1
  • 8
  • 10
  • 12
 12

Specifies the average minimum inter-packetgap (IPG) the IP core maintains on the TX Ethernet link.

The default value of 12 complies with the Ethernet standard.

The remaining values support increased throughput.
Additional IPG removed as per AM period Integer 0 Specifies the number of inter- packets gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance.
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