High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 4/29/2024
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide x
2.1. Creating an Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

2.5. Using the HBM2E Design Example with the Test Engine IP

  1. Click Tools > System Debugging Tools > System Console to open the System Console.
  2. Load the ed_synth.sof file into the System Console by clicking File > Load Design > ed_synth.sof. (Alternatively, you can load the .sof file from the terminal command line, if you prefer not to use the System Console.)
  3. After you have loaded the ed_synth.sof file, access the testengine_library.tcl file by entering the following command in the System Console:
    source hydra_sw/testengine_library.tcl
    You can see the test engine library loaded now. The testengine_library.tcl file includes the functions to interact with the test engine IP on hardware over a JTAG connection.
  4. Enter the following sequence of commands to check the driver status:
    1. To reset and program a new traffic pattern, type: testengine_reprogram
    2. To run the traffic, type: testengine_run
    3. To see the status of each driver included in the design, type: testengine_status
    For example, you should see the following output when you enabled all channels:
    Driver done: 16 / 16
Driver pass: 16 / 16

The above steps run the default traffic pattern self.hbm_simulation set in the traffic_pattern.py file located here: <example_design_directory>/qii/hydra_sw. You can change or customize the traffic pattern if you want. When you modify or use a new traffic pattern, you must first regenerate the driver files. Use the following command to regenerate the driver files for the new program: 

quartus_py hydra_sw/main.py --ipdir=<example_design_directory>/qii --prog=<name of your traffic pattern program>

The main advantage of the new test engine IP is that you don't need to recompile your entire design when you change or modify the traffic pattern. You must just regenerate the binary files. For additional information on test engine IP functions, refer to the testengine_library.tcl file.

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