High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 4/29/2024
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide x
2.1. Creating an Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example

Follow these steps to compile and program the design example in the Quartus® Prime software.
  1. To open the design example, click File > Open project, and navigate to the Quartus® Prime Pro Edition folder containing the design example directory, such as <project_directory>/<example_design_directory>/qii/ed_synth.qpf , and click Open.
  2. You can make the necessary pin assignments in the .qsf file or in the Pin Planner.
    (Refer to Top-Level Signals of the HBM2E Design Example for details on the reset and reference clock signals that require pin assignments.)
  3. To begin compilation, click Processing > Start Compilation. The successful completion of compilation generates a .sof file, which enables the design to run on hardware.
  4. To program your device with the compiled design, open the programmer by clicking Tools > Programmer.
  5. In the programmer, click Auto Detect to detect supported devices.
  6. Select the Agilex™ 7 M-series device and then select Change File.
  7. Navigate to the generated ed_synth.sof file and click Open.
  8. Click Start to begin programming the Agilex™ 7 M-series device. When the device is successfully programmed, the progress bar at the top-right of the window should indicate 100% (Successful).
For related information, refer to Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device in the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide.
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