High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 4/29/2024
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide x
2.1. Creating an Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor

You can use the Performance Monitor to check the performance metrics of each pesudo-channel or all eight channels.

To enable the Performance Monitor, select Enable Performance Monitoring on the Example Designs tab in the HBM2E parameter editor.

  1. Click Tools > System Debugging Tools > System Console to open the System Console.
  2. Load the ed_synth.sof file into the System Console by clicking File > Load Design > ed_synth.sof. (Alternatively, you can load the .sof file from the terminal command line, if you prefer not to use the System Console.)
  3. After you have loaded the ed_synth.sof file, access the testengine_library.tcl file by entering the following command in the System Console:
    source hydra_sw/testengine_library.tcl
    You can see the test engine library loaded now. The testengine_library.tcl file includes the functions to interact with the test engine IP on hardware over a JTAG connection.
  4. Load the pmon_library.tcl file in system-console by entering the following command: 
    source pmon_library.tcl
  5. Set the metric configuration on desired AXI4 performance monitors:
    pmon_set_all {config}
  6. Clear the counters and internal state of all performance monitors by typing the following command:
    pmon_reset_counter_data_all
  7. Reset and program a new traffic pattern by typing:
    testengine_reprogram
  8. Run traffic over the interface by typing: 
    testengine_run
  9. Read the metrics on the AXI4 performance monitor by typing: 
    pmon_read_all

The above steps are a recommended sequence of function calls to configure the Performance Monitor. For additional information on performance monitor functions available for your testing, refer to the pmon_library.tcl file.

The performance monitor reports the metrics measured at the Test Engine IP's AXI4 manager interface, and not at the memory interface.

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