High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 4/21/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
2.5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.5.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.5.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.5.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

3.3. Top-Level Signals of the HBM2E Design Example

Table 6.  Top-Level Signals
Signal Group Signal Name Direction Width Description
Clocks core_pll_refclk_clk Input 1 LVDS differential reference clock used by the I/O PLL to generate the fabric core clock. The design example automatically instantiates the I/O PLL that generates the core clock.
uibpll_refclk_clk Input 1 LVDS differential reference clock used by the UIB PLL. The design example automatically instantiates the UIB PLL that generates the clock for the UIB subsystem.
noc_clk_ctrl_refclk_clk Input 1

Single-ended reference clock used by the NoC PLL to generate the NoC clock. The design example automatically instantiates a NoC Clock Control block that contains the NoC PLL.

Resets global_user_reset_reset_n Input 1 Active-low asynchronous reset for the entire design example, including the UIB subsystem. When you make a pin assignment for this input, design rule checks may indicate that an input delay assignment is required. You can safely ignore these DRC warnings because the reset is fully asynchronous.
hbm_only_reset_reset Input 1 Active-high asynchronous reset for the HBM2E subsystem only. If you selected the Reset with Calibration reset type during HBM2E IP configuration, the HBM2E memory interface is calibrated. If you do not need to separately reset the HBM2E subsystem, you can tie this input low.
Special Signals for use by the Intel® Quartus® Prime software. hbm_cattrip_vitual_i_conduit Input 1 Special signal for internal use by the Intel® Quartus® Prime software. You cannot use this signal in any way, and it must be exported by the top level of your design.
hbm_temp _vitual_i_conduit Input 3 Special signal for internal use by the Intel® Quartus® Prime software. You cannot use this signal in any way, and it must be exported by the top level of your design.
Level Two Title