High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

Download PDF
ID 773266
Date 4/21/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
2.5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.5.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.5.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.5.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

3.2.2. Fabric NoC

You can generate either of the preceding use cases with the fabric NoC option. Enable the Use fabric NoC to return read responses via M20Ks parameter in the Example Design tab in the parameter editor to enable one of the Fabric NoC configurations.

The fabric NoC of the Intel Agilex® 7 M-Series FPGA enables AXI read response data to be delivered deep into the fabric using special routing in the M20K columns. This reduces the demand for fabric routing near the periphery of the device, and increases the bandwidth available for memory read responses. To support the increased read bandwidth, the NoC initiator IP provides a 512-bit wide AXI4 read data width. Throughput of the write data path can benefit from the saved routing resources if it is also configured to be 512 bits wide and the NoC initiator is supplied with an independent high-speed clock. These configurations enable the 512-bit wide data paths of the design example to saturate HBM2E sequential throughput at fabric frequencies of 350MHz or more (for -1 and -2 devices).

In a symmetrical data path configuration, the NoC Initiator IP has a single 512-bit wide AXI interface for both read and write data paths. This configuration is illustrated in the following figure. In this case you must supply the NoC bridge hardware with its own clock and reset signals.

Figure 7. Symmetrical 512-bit Wide Data Path Configuration

When the NoC Initiator is configured for symmetric 512-bit wide AXI4 interfaces, the mainband core clock drives these interfaces, and a separate NoC bridge fabric clock drives the initiator IP and the NoC initiator hardware. You can also configure the fabric NoC with asymmetric data paths where each read data path has is own clock, or you can drive both read and write data paths with the same clock.

The following illustration shows asymmetric fabric NoC configuration has separate clocks for read and write datapaths. By having a separate clock for the wider read data path, you can drive the 256-bit write data path with a faster clock which enables higher Fmax for the write interface, and hence improves the bandwidth. The following figure illustrates this configuration.

Figure 8. Asymmetrical Configuration with Read and Write Data Paths Driven by Separate Clocks
Figure 9.  Asymmetrical Configuration with Read and Write Data Paths Driven by the Same Clock

If Fabric NoC is enabled in the design, the NoC initiators that interface with the Fabric NoC cannot be used for AXI-lite transactions. Therefore, in designs using the Fabric NoC, the AXI-lite interface is supported through a dedicated NoC initiator; this is explained in more detail in the following section. For detailed information on the use of the fabric NoC, refer to the Fabric NoC Option section in the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide .

Level Two Title