High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 4/21/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
2.5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.5.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.5.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.5.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System

You must have an Intel® Quartus® Prime project before generating the HBM2E Intel FPGA IP and design example. If you do not already have an appropriate Intel® Quartus® Prime project, follow these steps to create an Intel® Quartus® Prime project targeting a device that supports High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP.
  1. Launch the Intel® Quartus® Prime Pro Edition software and select File > New Project Wizard. Click Next.
  2. Specify the project type, project directory, and device on this page.
  3. Verify that Empty Project is selected.
  4. Specify a directory name (<user project directory>), a name for the Intel® Quartus® Prime project (<user project name>), and a top-level design entity name (<user top-level instance name>) that you want to create.
  5. In the Device Family section of the dialog box, select Intel Agilex® 7 (F-Series/M-Series/I-Series).
  6. Under Device, select Intel Agilex® 7 M-Series which supports HBM2E. Alternatively, if you already know the specific part number of the device that you want to use, type that device part number in the Name filter field.
    Note: The generated HBM2E IP targets the specific Intel Agilex® 7 M-Series device that you specify. Because different Intel Agilex® 7 M-Series part numbers may identify devices with differing numbers of HBM2E devices and differing HBM2E device locations, as well as differing stack count, height, and density properties, it is important that you specify the correct Intel Agilex® 7 M-Series device part number before proceeding to the next step.
  7. Select the appropriate device under Available Devices. Click Next three times.
  8. Click Finish. The system creates the (<user project directory>).qpf and (<user project directory>).qsf files within the (<user project directory>).
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