Definitions

This document uses the following terminology:

• Hard Memory NoC – Network on a chip. A high-bandwidth interconnect.
• Initiator – Initiator NoC Interface Unit. An AXI bridge onto the NoC. The initiator is an AXI slave that converts AXI commands from a design in the FPGA fabric into NoC requests and converts NoC responses back into AXI responses delivered to the FPGA fabric.
• Target – Target NoC Interface Unit. A bridge from the NoC to an AXI target in the periphery of the FPGA device. The target is a NoC target and acts as an AXI master to a peripheral, such as a memory controller.

The HBM2E design example instantiates the following components and modules:

• An instance of the HBM2E IP that manages the read, write and other operations to the HBM2E DRAM device.
• NoC initiator IP which encapsulates initiators and fabric NoC adapter to bridge AXI4 commands from the traffic generators onto the hard memory NoC. The high speed interconnect NoC routes memory traffic from each initiator to the NoC targets that are bridges to the destination HBM pseudo-channels. Refer to the NoC Initiator IP section in the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide for information on the NoC initiator IP.
• The HBM traffic generator consists of two independent traffic drivers for every HBM2E channel enabled (one traffic driver for each HBM pseudo-channel). The traffic generator, known as the Test Engine Intel® FPGA IP, is a synthesizable AXI4 driver that generates a pseudo-sequential pattern of reads and writes to a parameterizable memory address range. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise.

  The traffic generator generates the sequential read and write traffic patterns in the HBM2E design example. You can select the number of reads and writes using the Select default traffic pattern parameter within the Example Design tab of the HBM2E Intel FPGA IP parameter editor. Each option generates following number of reads and writes:

  • Sequential Short – 2048 writes/reads
  • Sequential Medium - 25600 writes/reads
  • Sequential Long - 51200 writes/reads

  The generated traffic is routed to the initiators (which are part of the high-speed interconnect subsystem NoC) through their AXI interface. The NoC initiators and targets convert the AXI-based traffic to the hard memory NoC's own packet-based protocol. That traffic is routed through the NoC subsystem to appropriate targets. The targets convert the traffic back to AXI, for the HBM controller channels. The HBM controller converts AXI commands into HBM2E memory operations.

  Note: The current version of the Test Engine IP offers a preliminary feature set.
• A NoC clock control Intel® FPGA IP which is responsible for clocking the hard memory NoC. The hard memory NoC clock control IP also provides hard memory NoC performance monitoring registers.
• PLL, which generates the core clock (or clocks) used to clock the traffic generator and NoC Initiator IPs.
• A reset release Intel® FPGA IP which assists in correct sequencing of reset releases during device power-up and ensures that the design stays in reset until device power-up is completed.

If you enable the design for simulation, the HBM2E design example contains the following additional blocks:

• An HBM2E memory model.
• A simulation checker.
• The clock source and reset instances, which are bus functional models (BFMs) that generate the reference clock and reset signals.