High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 4/21/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
2.5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.5.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.5.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.5.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE

You can simulate your HBM2 EMIF IP using Mentor Graphics* ModelSim* software.
  1. Launch the Mentor Graphics* ModelSim* software and select File > Change Directory.
  2. Navigate to the <hbm_fp_0_example_design>/sim/ed_sim/mentor directory within the generated design example folder.
  3. Verify that the Transcript window is displayed at the bottom of the screen. If the Transcript window is not visible, display it by clicking View > Transcript.
  4. In the Transcript window, run source msim_setup.tcl. The simulation stops after the traffic generator test completes successfully.
  5. To generate simulation with detailed waveforms, rerun simulation by running ld_debug in the Transcript window.
  6. The Objects window displays the available signals from the design, once the ld_debug command has completed.
  7. In the Objects window, select the signals that you want to analyze in your simulation by right-clicking and selecting Add Wave.
  8. After you finish selecting the signals for simulation, execute run -all in the Transcript window. The simulation ends once the traffic generator test completes successfully.
Note: ModelSim* simulation of the HBM2E design example enabled with fabric NoC is supported only with the 2023 version of the ModelSim* software.
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