External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023
Public

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Document Table of Contents

6.1.1. Intel Agilex® 7 M-Series FPGA EMIF IP Parameter Descriptions for DDR4 Interfaces

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 53.  Group: Example Design / Example Design
Display Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

(Identifier: EX_DESIGN_HDL_FORMAT)

Synthesis

Generate Synthesis Example Design

(Identifier: EX_DESIGN_GEN_SYNTH)

Simulation

Generate Simulation Example Design

(Identifier: EX_DESIGN_GEN_SIM)

NOC Refclk Freq

NOC Refclk Freq for the NOC control IP

Note: This parameter can be auto-computed.

(Identifier: EX_DESIGN_NOC_REFCLK_FREQ_MHZ)

Hydra Remote Access

Specifies whether the Hydra control and status registers are accessible via JTAG, exported to the fabric, or just disabled

(Identifier: EX_DESIGN_HYDRA_REMOTE)

Table 54.  Group: General IP Parameters / High-Level Parameters
Display Name Description
Technology Generation

Denotes the specific memory technology generation to be used

Note: This parameter can be auto-computed.

(Identifier: MEM_TECHNOLOGY)

Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)

Memory Device Topology

Topology used by memory device

(Identifier: MEM_TOPOLOGY)

Memory Ranks

Total number of physical ranks in the interface

(Identifier: MEM_NUM_RANKS)

Device DQ Width

If the device is a DIMM: Specifies the full DQ width of the DIMM. In the case of DDR5 DIMM: If the DQ width is set to 32 bits, only 1 channel of the DIMM is used; If the DQ width is set to 64 bits, both channels of the DIMM are used.

If the interface is composed of discrete components: Specifies the DQ width of each discrete component.

(Identifier: MEM_DEVICE_DQ_WIDTH)

Number of Components Per Rank

Number of components per rank. If each component contains more than one rank, then set this parameter to 1.

(Identifier: MEM_COMPS_PER_RANK)

Force Ranks to Share One Memory Interface Clock

Specifies whether all the ranks in the same channel should share one pair of memory interface differential clock. Applicable to DDR4 only.

(Identifier: MEM_RANKS_SHARE_CLOCKS)

ECC Mode

Specifies the type of ECC (if any) and the required number of side-band bits that will be used by this EMIF instance. While not all required side-band bits necessarily carry ECC bits, all need to be connected to the memory device. If enabling ECC requires more side-band bits than necessary ECC bits, then ECC bits are transmitted on the least significant side-band bits.

Note: This parameter can be auto-computed.

(Identifier: CTRL_ECC_MODE)

Enable Extra DQ Byte Lane

Augment a given memory interface with 8 extra DQ bits. These extra bits are accessed via the WUSER and RUSER ports on the PHY's AXI4 interface. The AXI4 WUSER and RUSER ports are 64-bit wide. In this release, this option can only augment a given 32/64-bit DDR4 in interface configured in fabric-synchronous mode without controller generated ECC bits.

Note: This parameter can be auto-computed.

(Identifier: AXI4_USER_DATA_ENABLE)

Total DQ Width

(Derived Parameter) This will be the width (in bits) of the mem_dq port on the memory interface.

For a component interface, it is calculated based on: (MEM_COMPS_PER_RANK * MEM_DEVICE_DQ_WIDTH + (8 bits if Side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode)) * MEM_NUM_CHANNELS

For a DIMM-based interface, it is just MEM_DEVICE_DQ_WIDTH + (8 bits if side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode) * MEM_NUM_CHANNELS.

(Identifier: MEM_TOTAL_DQ_WIDTH)

Alert_N Pin Placement

(DDR4 only) Specifies the AC lane index in which to place the ALERT_N pin.

(Identifier: PHY_ALERT_N_PLACEMENT)

Minimum Number of AC Lanes for DDR4

Specifies the minimum number of AC lanes required for the memory interface. Only applicable for DDR4.

(Identifier: USER_MIN_NUM_AC_LANES)

Memory Clock Frequency

Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FREQ_MHZ)

Instance ID

Instance ID of the EMIF IP. EMIF in the same bank, or connected to related user logic (e.g. to the same INIU), should have unique IDs in order to distinguish them when using the side-band interface. Valid values are 0-6.

(Identifier: INSTANCE_ID)

Table 55.  Group: General IP Parameters / Memory Device Preset Selection
Display Name Description
Use Memory Device Preset from file

Specifies whether MEM_PRESET_ID will be a value from Quartus (if false), or a value from a custom preset file path (if true)

(Identifier: MEM_PRESET_FILE_EN)

Memory Preset custom file path

Path to a .qprs file on the users disk

(Identifier: MEM_PRESET_FILE_QPRS)

Memory Preset

The name of a preset that the user would like to load, describing the memory device that this emif will be targeting.

Note: This parameter can be auto-computed.

(Identifier: MEM_PRESET_ID)

Table 56.  Group: General IP Parameters / Advanced Parameters / PHY / Topology
Display Name Description
Use NOC

Specifies whether we are using the NOC or bypassing it

Note: This parameter can be auto-computed.

(Identifier: PHY_NOC_EN)

Asynchronous Enable

Specifies whether the user logic is clocked based on the clock provided by the IP (Sync), or by a separate user clock (Async). If true - async mode is used, if false - sync mode is used.

(Identifier: PHY_ASYNC_EN)

AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms IO BANK and TOP vs BOT part of the IO BANK). Legal ranges are derived from device floorplan. By default (value=AUTO), the most optimal location is selected (to maximize available frequency and data width).

Note: This parameter can be auto-computed.

(Identifier: PHY_AC_PLACEMENT)

PLL Reference Clock Frequency

Specifies what PLL reference clock frequency the user will supply. It is recommended to use the fastest possible PLL reference clock frequency because it leads to better jitter performance.

Note: This parameter can be auto-computed.

(Identifier: PHY_REFCLK_FREQ_MHZ)

Table 57.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings
Display Name Description
Voltage

The voltage level for the I/O pins driving the signals between the memory device and the FPGA memory interface.

(Identifier: PHY_IO_VOLTAGE)

Table 58.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Address/Command
Display Name Description
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the Address/Command Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: R_S_PHY_AC_OUTPUT_OHM)

Table 59.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Memory Clock
Display Name Description
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: R_S_PHY_CK_OUTPUT_OHM)

Table 60.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Data Bus
Display Name Description
I/O Standard

Specifies the I/O electrical standard for the data bus pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard.

(Identifier: PHY_DQ_IO_STD_TYPE)

Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: R_S_PHY_DQ_OUTPUT_OHM)

Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

(Identifier: PHY_DQ_SLEW_RATE)

Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: R_T_PHY_DQ_INPUT_OHM)

Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

(Identifier: PHY_DQ_VREF)

Table 61.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / PHY Inputs
Display Name Description
PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: R_T_PHY_REFCLK_INPUT_OHM)

Table 62.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Data Bus On-Die Termination (ODT)
Display Name Description
Target Write Termination

Specifies the target termination to be used during a write

(Identifier: MEM_ODT_TGT_WR)

Non-Target Write Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a write

(Identifier: MEM_ODT_NON_TGT_WR)

Non-Target Read Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a read

(Identifier: MEM_ODT_NON_TGT_RD)

Drive Strength

Specifies the termination to be used when driving read data from memory

(Identifier: MEM_RON)

Table 63.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Data Bus Reference Voltage (Vref)
Display Name Description
VrefDQ Range

Specifies which of the memory protocol defined ranges will be used

(Identifier: MEM_DQ_VREF_RANGE)

VrefDQ Value

Specifies the initial VrefDQ value to be used

(Identifier: MEM_DQ_VREF_VALUE)

Table 64.  Group: General IP Parameters / Advanced Parameters / AXI Settings / AXI Interface Settings
Display Name Description
Enable Debug Tools

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

(Identifier: DEBUG_TOOLS_EN)

AXI-Lite Port Access Mode

Specifies whether the AXI-Lite port is connected to the fabric, the NOC, or disabled

Note: This parameter can be auto-computed.

(Identifier: AXI_SIDEBAND_ACCESS_MODE)

Table 65.  Group: General IP Parameters / Advanced Parameters / Additional Parameters / Additional String Parameters
Display Name Description
User Extra Parameters

Semi-colon separated list of key/value pairs of extra parameters

(Identifier: USER_EXTRA_PARAMETERS)