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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
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3.4. Intel Agilex® 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
The Intel Agilex® 7 M-Series FPGA EMIF IP can enable the Intel Agilex® 7 FPGA hard processor subsystem (HPS) to access external DRAM memory devices.
To enable connectivity between the HPS and the Intel Agilex® 7 M-Series EMIF IP, you must create and configure an instance of the EMIF for HPS IP, and connect it to the Intel Agilex® 7 FPGA hard processor subsystem instance in your system.
Restrictions on I/O Bank Usage for Intel Agilex® 7 M-Series EMIF IP with HPS
Only the two IO96 banks adjacent to the HPS MPFE can be used for HPS-EMIF (bank 3C and bank 3D. The following restrictions apply to the I/O bank usage:
- If one IO96 bank is to be used by HPS-EMIF, it must be the one adjacent to the HPS MPFE (bank 3D).
- No protocol's data width usage may span multiple IO96 banks. For example, a single DDR4 x64, which requires 8 byte lanes for data and 3 byte lanes for address and control, may not span two IO96 banks. However, a single DDR4 x32, which requires 4 byte lanes of data and 3 byte lanes of address and control, may be placed in one IO96 bank, and another single DDR4 x32, may be placed in another IO96 ban.
- Unused pins in an HPS-EMIF occupied IO96 bank must be left unused; you cannot use them as general-purpose I/O pins.
- Unused lanes in an HPS-EMIF occupied IO96 bank should be left unconnected; you cannot use them as general-purpose I/O pins.
- Reference clock sharing is not allowed between HPS-EMIF IP and other IPs.
- For multi-channel EMIFs or when multiple EMIFs are used inside HPS-EMIF IP, they must have identical IP parameters.
- Initiators and targets must only be connected according to the following table:
HPS Initiator Non-HPS Initiator HPS Initiator-lite Non-HPS Initiator-lite HPS EMIF Target Yes No — — Non-HPS EMIF Target No Yes — — HPS EMIF Target-lite — — Yes * No Non-HPS EMIF Target-lite — — No Yes Note: * The Intel® Quartus® Prime software may make this connection automatically.
Data Width Usage | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|
DDR4 | ||||||||
DDR4x16 | — | — | — | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
DDR4x16+ECC | — | — | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
DDR4x32 | — | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
DDR4x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
DDR4x64 | NO | |||||||
DDR4x64+ECC | NO | |||||||
DDR5 | ||||||||
DDR5x16 | — | — | — | — | AC1 | AC0 | DQ[0] | DQ[1] |
DDR5x16 | DQ[1] | DQ[0] | AC1 | AC0 | — | — | — | — |
DDR5 2chx16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] |
DDR5x16+ECC | — | — | — | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] |
DDR5x32 | — | — | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] |
DDR5x32+ECC | — | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] |
LPDDR5 | ||||||||
LPDDR5x16 | — | — | — | — | AC1 | AC0 | DQ[1] | DQ[0] |
LPDDR5x16 | DQ[1] | DQ[0] | AC1 | AC0 | — | — | — | — |
LPDDR5 2chx16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] |
LPDDR5x32 | DQ[3] | DQ[2] | — | — | AC1 | AC0 | DQ[1] | DQ[0] |