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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
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3.1.3.3. LPDDR5 Pin Placement
Lane Number | Pin Index | x32 | 2 Channel x16 |
---|---|---|---|
BL7 | 95 | MEM_DQ[31] | MEM_1_MEM_DQ[15] |
94 | MEM_DQ[30] | MEM_1_MEM_DQ[14] | |
93 | MEM_DQ[29] | MEM_1_MEM_DQ[13] | |
92 | MEM_DQ[28] | MEM_1_MEM_DQ[12] | |
91 | |||
90 | MEM_DMI[3] | MEM_1_MEM_DMI[1] | |
89 | MEM_RDQS_C[3] | MEM_1_MEM_RDQS_C[1] | |
88 | MEM_RDQS_T[3] | MEM_1_MEM_RDQS_T[1] | |
87 | MEM_DQ[27] | MEM_1_MEM_DQ[11] | |
86 | MEM_DQ[26] | MEM_1_MEM_DQ[10] | |
85 | MEM_DQ[25] | MEM_1_MEM_DQ[9] | |
84 | MEM_DQ[24] | MEM_1_MEM_DQ[8] | |
BL6 | 83 | MEM_DQ[23] | MEM_1_MEM_DQ[7] |
82 | MEM_DQ[22] | MEM_1_MEM_DQ[6] | |
81 | MEM_DQ[21] | MEM_1_MEM_DQ[5] | |
80 | MEM_DQ[20] | MEM_1_MEM_DQ[4] | |
79 | |||
78 | MEM_DMI[2] | MEM_1_MEM_DMI[0] | |
77 | MEM_RDQS_C[2] | MEM_1_MEM_RDQS_C[0] | |
76 | MEM_RDQS_T[2] | MEM_1_MEM_RDQS_T[0] | |
75 | MEM_DQ[19] | MEM_1_MEM_DQ[3] | |
74 | MEM_DQ[18] | MEM_1_MEM_DQ[2] | |
73 | MEM_DQ[17] | MEM_1_MEM_DQ[1] | |
72 | MEM_DQ[16] | MEM_1_MEM_DQ[0] | |
BL5 | 71 | ||
70 | |||
69 | |||
68 | MEM_1_MEM_CS[1] | ||
67 | MEM_1_CK_C | ||
66 | MEM_1_CK_T | ||
65 | MEM_1_MEM_CS[0] | ||
64 | MEM_1_MEM_CA[6] | ||
63 | MEM_1_RESET_N | ||
62 | OCT_1_OCT_RZQIN | ||
61 | |||
60 | |||
BL4 | 59 | Differential "NSide" Reference Clock Input Site |
|
58 | Differential "PSide" Reference Clock Input Site |
||
57 | MEM_1_MEM_CA[5] | ||
56 | MEM_1_MEM_CA[4] | ||
55 | MEM_1_MEM_WCK_C[1] | ||
54 | MEM_1_MEM_WCK_T[1] | ||
53 | MEM_1_MEM_WCK_C[0] | ||
52 | MEM_1_MEM_WCK_T[0] | ||
51 | MEM_1_MEM_CA[3] | ||
50 | MEM_1_MEM_CA[2] | ||
49 | MEM_1_MEM_CA[1] | ||
48 | MEM_1_MEM_CA[0] | ||
BL3 | 47 | ||
46 | |||
45 | |||
44 | MEM_CS[1] | MEM_0_MEM_CS[1] | |
43 | MEM_CK_C | MEM_0_CK_C | |
42 | MEM_CK_T | MEM_0_CK_T | |
41 | MEM_CS[0] | MEM_0_MEM_CS[0] | |
40 | MEM_CA[6] | MEM_0_MEM_CA[6] | |
39 | MEM_RESET_N | MEM_0_RESET_N | |
38 | RZQ Site | OCT_0_OCT_RZQIN | |
37 | |||
36 | |||
BL2 | 35 | Differential "N-Side" Reference Clock Input Site | Differential "NSide" Reference Clock Input Site |
34 | Differential "P-Side" Reference Clock Input Site | Differential "PSide" Reference Clock Input Site |
|
33 | MEM_CA[5] | MEM_0_MEM_CA[5] | |
32 | MEM_CA[4] | MEM_0_MEM_CA[4] | |
31 | MEM_WCK_C[1] | MEM_0_MEM_WCK_C[1] | |
30 | MEM_WCK_T[1] | MEM_0_MEM_WCK_T[1] | |
29 | MEM_WCK_C[0] | MEM_0_MEM_WCK_C[0] | |
28 | MEM_WCK_T[0] | MEM_0_MEM_WCK_T[0] | |
27 | MEM_CA[3] | MEM_0_MEM_CA[3] | |
26 | MEM_CA[2] | MEM_0_MEM_CA[2] | |
25 | MEM_CA[1] | MEM_0_MEM_CA[1] | |
24 | MEM_CA[0] | MEM_0_MEM_CA[0] | |
BL1 | 23 | MEM_DQ[15] | MEM_0_MEM_DQ[15] |
22 | MEM_DQ[14] | MEM_0_MEM_DQ[14] | |
21 | MEM_DQ[13] | MEM_0_MEM_DQ[13] | |
20 | MEM_DQ[12] | MEM_0_MEM_DQ[12] | |
19 | |||
18 | MEM_DMI[1] | MEM_0_MEM_DMI[1] | |
17 | MEM_RDQS_C[1] | MEM_0_MEM_RDQS_C[1] | |
16 | MEM_RDQS_T[1] | MEM_0_MEM_RDQS_T[1] | |
15 | MEM_DQ[11] | MEM_0_MEM_DQ[11] | |
14 | MEM_DQ[10] | MEM_0_MEM_DQ[10] | |
13 | MEM_DQ[9] | MEM_0_MEM_DQ[9] | |
12 | MEM_DQ[8] | MEM_0_MEM_DQ[8] | |
BL0 | 11 | MEM_DQ[7] | MEM_0_MEM_DQ[7] |
10 | MEM_DQ[6] | MEM_0_MEM_DQ[6] | |
9 | MEM_DQ[5] | MEM_0_MEM_DQ[5] | |
8 | MEM_DQ[4] | MEM_0_MEM_DQ[4] | |
7 | |||
6 | MEM_DMI[0] | MEM_0_MEM_DMI[0] | |
5 | MEM_RDQS_C[0] | MEM_0_MEM_RDQS_C[0] | |
4 | MEM_RDQS_T[0] | MEM_0_MEM_RDQS_T[0] | |
3 | MEM_DQ[3] | MEM_0_MEM_DQ[3] | |
2 | MEM_DQ[2] | MEM_0_MEM_DQ[2] | |
1 | MEM_DQ[1] | MEM_0_MEM_DQ[1] | |
0 | MEM_DQ[0] | MEM_0_MEM_DQ[0] |