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1. Intel® FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial
4. Intel® FPGA AI Suite SoC Design Example Run Process
5. Intel® FPGA AI Suite SoC Design Example Build Process
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture
7. Intel® FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. Intel® FPGA AI Suite SoC Design Example User Guide Archives
B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing SoC FPGA Development Kits for the Intel® FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Verifying FPGA Device Drivers
3.8. Running the Demonstration Applications
3.5.1.1. Confirming Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit Board Set Up
3.5.1.2. Programming the Intel Agilex® 7FPGA Device with the JTAG Indirect Configuration (.jic) File
3.5.1.3. Connecting the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit to the Host Development System
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend
7.1.6. Yocto Recipe: wic
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3.8.1. Running the M2M Mode Demonstration Application
The M2M dataflow model uses the dla_benchmark demonstration application. The S2M bitstream supports both the M2M dataflow model and the S2M dataflow model.
You must know the host name of the SoC FPGA development kit. If you do not know the development kit host name, go back to Determining the SoC FPGA Development Kit IP Address before continuing here.
To run inference on the SoC FPGA development kit:
- Open an SSH connection to the SoC FPGA development kit:
- Start a new terminal session
- Run the following command:
build-host:$ ssh <devkit_hostname>
Where <devkit_hostname> is the host name you determined in Determining the SoC FPGA Development Kit IP Address.
Continuing the example from Determining the SoC FPGA Development Kit IP Address, the following command would open an SSH connection:build-host:$ ssh arria10-62747948036a.local
- In the SSH terminal, run the following commands:
export compiled_model=~/resnet-50-tf/RN50_Performance_b1.bin export imgdir=~/resnet-50-tf/sample_images export archfile=~/resnet-50-tf/<architecture file> cd ~/app export COREDLA_ROOT=/home/root/app ./dla_benchmark \ -b=1 \ -cm $compiled_model \ -d=HETERO:FPGA,CPU \ -i $imgdir \ -niter=5 \ -plugins_xml_file ./plugins.xml \ -arch_file $archfile \ -api=async \ -groundtruth_loc $imgdir/TF_ground_truth.txt \ -perf_est \ -nireq=4 \ -bgr
where <architecture file> is one of the following files, depending on your development kit:- Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit
AGX7_Performance.arch
- Intel® Arria® 10 SX SoC FPGA Development Kit
A10_Performance.arch
- Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit
The dla_benchmark command generates output similar to the following example output for each step:
[Step 11/12] Dumping statistics report count: 8 iterations system duration: 174.3530 ms IP duration: 112.1184 ms latency: 79.9449 ms system throughput: 45.8839 FPS number of hardware instances: 1 number of network instances: 1 IP throughput per instance: 71.3531 FPS IP throughput per fmax per instance: 0.3568 FPS/MHz IP clock frequency: 200.0000 MHz [Step 12/12] Dumping the output values [ INFO ] Dumping result of Graph_0 to result.txt and result_tensor_boundaries.txt