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1. Intel® FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial
4. Intel® FPGA AI Suite SoC Design Example Run Process
5. Intel® FPGA AI Suite SoC Design Example Build Process
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture
7. Intel® FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. Intel® FPGA AI Suite SoC Design Example User Guide Archives
B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing SoC FPGA Development Kits for the Intel® FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Verifying FPGA Device Drivers
3.8. Running the Demonstration Applications
3.5.1.1. Confirming Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit Board Set Up
3.5.1.2. Programming the Intel Agilex® 7FPGA Device with the JTAG Indirect Configuration (.jic) File
3.5.1.3. Connecting the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit to the Host Development System
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend
7.1.6. Yocto Recipe: wic
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3.6.4. Copying the Compiled Graphs to the SD card
To copy the required demonstration files to the /home/root/resnet-50-tf folder on the SD card:
- In the serial console, create directories to receive the model data and sample images:
mkdir ~/resnet-50-tf
- On the development host, use the secure copy (scp) command to copy the data to the board:
TARGET_IP=<Development Kit Hostname>.local TARGET=”root@$TARGET_IP:~/resnet-50-tf” demodir=$COREDLA_WORK/demo scp $demodir/*.bin $TARGET/. scp -r $demodir/sample_images/ $TARGET/. scp $COREDLA_ROOT/example_architectures/<architecture file> $TARGET/. scp $COREDLA_ROOT/build_os.txt $TARGET/../app/
where <architecture file> is one of the following files, depending on your development kit:- Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit
AGX7_Performance.arch
- Intel® Arria® 10 SX SoC FPGA Development Kit
A10_Performance.arch
- Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit
- [Optional] In the serial console run the sync command to ensure that the data is flushed to disk.