Intel® FPGA AI Suite: SoC Design Example User Guide

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ID 768979
Date 2/12/2024
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite SoC Design Example User Guide 2. About the SoC Design Example 3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial 4. Intel® FPGA AI Suite SoC Design Example Run Process 5. Intel® FPGA AI Suite SoC Design Example Build Process 6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture 7. Intel® FPGA AI Suite Soc Design Example Software Components 8. Streaming-to-Memory (S2M) Streaming Demonstration A. Intel® FPGA AI Suite SoC Design Example User Guide Archives B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History
2. About the SoC Design Example x
2.1. Intel® FPGA AI Suite SoC Design Example Prerequisites
2.1. Intel® FPGA AI Suite SoC Design Example Prerequisites x
2.1.1. Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit Hardware Requirements
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial x
3.1. Initial Setup 3.2. Initializing a Work Directory 3.3. (Optional) Create an SD Card Image (.wic) 3.4. Writing the SD Card Image (.wic) to an SD Card 3.5. Preparing SoC FPGA Development Kits for the Intel® FPGA AI Suite SoC Design Example 3.6. Adding Compiled Graphs (AOT files) to the SD Card 3.7. Verifying FPGA Device Drivers 3.8. Running the Demonstration Applications
3.3. (Optional) Create an SD Card Image (.wic) x
3.3.1. Installing Prerequisite Software for Building an SD Card Image 3.3.2. Building the FPGA Bitstreams 3.3.3. Installing HPS Disk Image Build Prerequisites 3.3.4. (Optional) Downloading the ImageNet Categories 3.3.5. Building the SD Card Image
3.5. Preparing SoC FPGA Development Kits for the Intel® FPGA AI Suite SoC Design Example x
3.5.1. Preparing the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit 3.5.2. Preparing the Intel® Arria® 10 SX SoC FPGA Development Kit 3.5.3. Configuring the SoC FPGA Development Kit UART Connection 3.5.4. Determining the SoC FPGA Development Kit IP Address
3.5.1. Preparing the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit x
3.5.1.1. Confirming Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit Board Set Up 3.5.1.2. Programming the Intel Agilex® 7FPGA Device with the JTAG Indirect Configuration (.jic) File 3.5.1.3. Connecting the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit to the Host Development System
3.5.2. Preparing the Intel® Arria® 10 SX SoC FPGA Development Kit x
3.5.2.1. Confirming Intel® Arria® 10 SX SoC FPGA Development Kit Board Settings 3.5.2.2. Connecting the Intel® Arria® 10 SX SoC FPGA Development Kit to the Host Development System
3.6. Adding Compiled Graphs (AOT files) to the SD Card x
3.6.1. Preparing OpenVINO™ Model Zoo 3.6.2. Preparing a Model 3.6.3. Compiling the Graphs 3.6.4. Copying the Compiled Graphs to the SD card
3.8. Running the Demonstration Applications x
3.8.1. Running the M2M Mode Demonstration Application 3.8.2. Running the S2M Mode Demonstration Application 3.8.3. Troubleshooting the Demonstration Applications
4. Intel® FPGA AI Suite SoC Design Example Run Process x
4.1. Exporting Trained Graphs from Source Frameworks 4.2. Compiling Exported Graphs Through the Intel® FPGA AI Suite
5. Intel® FPGA AI Suite SoC Design Example Build Process x
5.1. Building the Intel® Quartus® Prime Project 5.2. Building the Bootable SD Card Image (.wic)
5.1. Building the Intel® Quartus® Prime Project x
5.1.1. Intel® Quartus® Prime Build Flow 5.1.2. Build Script Options 5.1.3. Build Directory
5.1.1. Intel® Quartus® Prime Build Flow x
5.1.1.1. Build Synchronization of FPGA with Software
5.1.3. Build Directory x
5.1.3.1. The create_project.bash Script 5.1.3.2. The generate_sof.bash Script 5.1.3.3. The generate_rbf.bash Script 5.1.3.4. The build_stream_controller.sh Script
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture x
6.1. Intel® FPGA AI Suite SoC Design Example Inference Sequence Overview 6.2. Memory-to-Memory (M2M) Variant Design 6.3. Streaming-to-Memory (S2M) Variant Design 6.4. Top Level 6.5. The SoC Design Example Platform Designer System 6.6. Fabric EMIF Design Component 6.7. PLL Configuration
6.2. Memory-to-Memory (M2M) Variant Design x
6.2.1. The mSGDMA Intel FPGA IP 6.2.2. RAM considerations
6.3. Streaming-to-Memory (S2M) Variant Design x
6.3.1. Streaming Enablement for Intel® FPGA AI Suite 6.3.2. Nios® V Subsystem 6.3.3. Streaming System Operation 6.3.4. Resolving Input Rate Mismatches Between the Intel® FPGA AI Suite IP and the Streaming Input 6.3.5. The Layout Transform IP as an Application-Specific Block
6.3.3. Streaming System Operation x
6.3.3.1. Streaming System Buffer Management 6.3.3.2. Streaming System Inference Job Management
6.3.5. The Layout Transform IP as an Application-Specific Block x
6.3.5.1. Layout Transform Considerations 6.3.5.2. Layout Transform IP Register Map 6.3.5.3. Layout Transform Configuration Options
6.4. Top Level x
6.4.1. Clock Domains
6.5. The SoC Design Example Platform Designer System x
6.5.1. The dla_0 Platform Designer Layer (dla.qsys) 6.5.2. The hps_0 Platform Designer Layer (hps.qys)
7. Intel® FPGA AI Suite Soc Design Example Software Components x
7.1. Yocto Build and Runtime Linux Environment 7.2. Intel® FPGA AI Suite Runtime Plugin 7.3. Runtime Interaction with the MMD Layer 7.4. MMD Layer Hardware Interaction Library
7.1. Yocto Build and Runtime Linux Environment x
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb 7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend 7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb 7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb 7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend 7.1.6. Yocto Recipe: wic
7.4. MMD Layer Hardware Interaction Library x
7.4.1. MMD Layer Hardware Interaction Library Class mmd_device 7.4.2. MMD Layer Hardware Interaction Library Class uio_device 7.4.3. MMD Layer Hardware Interaction Library Class dma_device
8. Streaming-to-Memory (S2M) Streaming Demonstration x
8.1. Nios® Subsystem 8.2. Building the Stream Controller Module 8.3. Building the Streaming Demonstration Applications 8.4. Running the Streaming Demonstration
8.1. Nios® Subsystem x
8.1.1. Stream Controller Communication Protocol 8.1.2. Buffer Flow in Streaming Mode using Nios® V Software Scheduler
8.1.2. Buffer Flow in Streaming Mode using Nios® V Software Scheduler x
8.1.2.1. Review of M2M mode 8.1.2.2. External Streaming Mode Buffer Flow 8.1.2.3. Nios® V Stream Controller State Machine Buffer Flow
8.4. Running the Streaming Demonstration x
8.4.1. The streaming_inference_app Application 8.4.2. The image_streaming_app Application
1. Intel® FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial
4. Intel® FPGA AI Suite SoC Design Example Run Process
5. Intel® FPGA AI Suite SoC Design Example Build Process
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture
7. Intel® FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. Intel® FPGA AI Suite SoC Design Example User Guide Archives
B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History

3.5.4. Determining the SoC FPGA Development Kit IP Address

To determine the FPGA development kit IP address:
  1. Open a Terminal session to the FPGA development kit via the UART connection and log in using the user name root and no password.
             Starting Record Runlevel Change in UTMP…
[  OK  ] Finished Record Runlevel Change in UTMP.
     9.553286] random: crng init done
[  OK  ] Finished Load/Save Random Seed.
[   10.084845] socfpga-dwmax ff800000.ethernet eth0: Link is Up – 1Gbps/Full – flow control off
[   10.103287] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Poky (Yocto Project Reference Distro) 4.0.2 arria10-62747948036a ttyS0

arria10-62747948036a login:
  2. Issue a hostname command to display the network name of the FPGA development kit board:
    root@arria10-62747948036a:~# hostname
arria10-62747948036a
root@arria10-62747948036a:~#

    In this example, the network name of the board is arria10-62747948036a.

    Tip: You need this hostname later on to open an SSH connection to the FPGA development kit.
  3. Confirm that you have a connection to the development kit from the development host with the ping command. Append the .local to the host name when you issue the ping command:
    build-host:$ ping arria10-62747948036a.local -c4
PING arria10-62747948036a (192.168.0.23) 56(84) bytes of data.
64 bytes of data from arria10-62747948036a (192.168.0.23): icmp_seq=1 ttl=63 time=1.66ms
64 bytes of data from arria10-62747948036a (192.168.0.23): icmp_seq=1 ttl=63 time=1.66ms
64 bytes of data from arria10-62747948036a (192.168.0.23): icmp_seq=1 ttl=63 time=1.66ms
64 bytes of data from arria10-62747948036a (192.168.0.23): icmp_seq=1 ttl=63 time=1.66ms

--- arria10-62747948036a ping statistics ---
4 packets transmitted, 4 received, 0% packet loss, time 3005ms
rtt min/avg/max/mdev = 1.664/2.037/2.283/0.238 ms

You can use the host name when you need to transfer files to the running system by appending the .local to the host name. For example, for the host name arria10-62747948036a, you can use arria10-62747948036a.local.

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