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1. Intel® FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial
4. Intel® FPGA AI Suite SoC Design Example Run Process
5. Intel® FPGA AI Suite SoC Design Example Build Process
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture
7. Intel® FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. Intel® FPGA AI Suite SoC Design Example User Guide Archives
B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing SoC FPGA Development Kits for the Intel® FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Verifying FPGA Device Drivers
3.8. Running the Demonstration Applications
3.5.1.1. Confirming Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit Board Set Up
3.5.1.2. Programming the Intel Agilex® 7FPGA Device with the JTAG Indirect Configuration (.jic) File
3.5.1.3. Connecting the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit to the Host Development System
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend
7.1.6. Yocto Recipe: wic
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3.5.1.2. Programming the Intel Agilex® 7FPGA Device with the JTAG Indirect Configuration (.jic) File
To program the Intel Agilex® 7 FPGA device with the JTAG indirect configuration (.jic) file:
- Connect the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit to your host development system via USB 2.0 connection as shown in the following diagram:
- Program the QSPI with the .jic file by running the following commands on the host development system:
cd $COREDLA_ROOT/demo/ed4/agx7_soc_s2m/sd-card/ quartus_pgm -m jtag -o "pvi;u-boot-spl-dtb.hex.jic@<device_number>"
where <device_number> is 1 or 2, depending on whether the HPS is already running (that is, the prior state of the device). Use 1 if the HPS is not running, and 2 if the HPS is already running. If you do not know the state of the device, try 1. If that fails, try 2.The Intel Agilex® 7FPGA device is configured from the QSPI flash at boot time.