Intel® FPGA AI Suite: IP Reference Manual

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ID 768974
Date 7/03/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite IP Reference Manual 2. About the Intel® FPGA AI Suite IP 3. Intel® FPGA AI Suite IP Generation Utility 4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. Intel® FPGA AI Suite IP Reference Manual Archives B. Intel® FPGA AI Suite IP Reference Manual Document Revision History
2. About the Intel® FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Intel® FPGA AI Suite Layer / Primitive Ranges 2.4. Intel® FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. Intel® FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter group: Global Parameters 2.4.2.2. Parameter group: activation 2.4.2.3. Parameter group: pe_array 2.4.2.4. Parameter group: pool 2.4.2.5. Module: softmax 2.4.2.6. Parameter group: dma 2.4.2.7. Parameter group: xbar 2.4.2.8. Parameter group: filter_scratchpad 2.4.2.9. Parameter group: config_network
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping
3. Intel® FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
The --flow Option The --arch Option The --arch_dir Option The --ip_dir Option The --unlicenced/--licenced Options The --overwrite Option 3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers
1. Intel® FPGA AI Suite IP Reference Manual
2. About the Intel® FPGA AI Suite IP
3. Intel® FPGA AI Suite IP Generation Utility
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. Intel® FPGA AI Suite IP Reference Manual Archives
B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

3.4. IP Generation Utility Command Line Options

The actions of the IP generation utility (dla_create_ip command) are controlled primarily by the --flow option. Depending on your choice for the --flow option, you might need to specify other command options.

The --flow Option

This option specifies the IP generation utility execution flow to run.

Syntax
--flow <flow>

Where <flow> specifies the execution flow to run.

Valid values
Default Value
create_ip

The --arch Option

This option specifies one or more Intel® FPGA AI Suite architecture description files (.arch) to use in the flow.

If you specify this option, you cannot specify the --arch_dir option.

Syntax
--arch <architecture> [<architecture2>] [<architecture3] ...

For the create_ip and add_arch flows, specify a path to the architecture description file or files to add to an IP library.

For the remove_arch flow, specify the name of the architecture description file or files to remove from an IP library.

The --arch_dir Option

Use this option with the create_ip and add_arch flows to specify the path to a directory that contains architecture description files. If you specify this option, the IP generation utility adds each architecture in the specified directory to the Intel® FPGA AI Suite IP library.

If you specify this option, you cannot specify the --arch option.

Syntax
--arch_dir <path_to_arch_folder>

The --ip_dir Option

This option specifies the path of the Intel® FPGA AI Suite IP library directory to use in the flow.

In the create_ip flow, this directory is created if it does not exist. For all other flows, the specified IP library directory must exist.

Syntax
--ip_dir <ip_directory>
Default Value
<ai_suite_root>/ip

The --unlicenced/--licenced Options

Generate an unlicensed or licensed copy of the Intel® FPGA AI Suite IP:
  • Unlicensed IP: Unlicensed IP has a limit of 10000 inferences. After 10000 inferences, the unlicensed IP refuses to perform any additional inference and a bit in the CSR is set. For details about the CSR bit, refer to DMA Descriptor Queue.
  • Licensed IP: Licensed IP has no inference limitation.

If you generate a licensed copy of the IP but do not have a license, then Quartus cannot to generate a programming bitstream for your FPGA.

If neither option is specified, then the tool queries the lmutil license manager to determine the correct option.

Syntax

--unlicenced

--licenced

The --overwrite Option

For the create_ip flow, use this option to overwrite the IP library directory when you specify an existing IP library directory.

If you specify an existing directory with the create_ip flow and do not specify the --overwrite option, you are asked if you want to overwrite the directory.

Syntax
--overwrite

Section Content
The --flow create_ip Flow
The --flow add_arch Flow
The --flow list Flow
The --flow remove_arch Flow

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