Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 7/03/2023
Public

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5.2. Interrupt Control

The interrupt control feature registers are as follows:

Table 10.  Interrupt Control Feature Registers

Register

Offset

Attribute

Description

ICR

0x000

RW1C

DMA Interrupt control register

IMR

0x004

RW

DMA Interrupt mask register

The DMA optionally generates level sensitive interrupt signals in response to various events.

The hardware sets the corresponding bit within the ICR register whenever such an event occurs.

An interrupt is generated upon a 0-to-1 transition of a bit within ICR only if the corresponding bit in the IMR is set to one. A 0-to-1 transition of a bit within the IMR also generates an interrupt if the corresponding bit within the ICR is set to 1.

Table 11.  Interrupt Control Register (ICR) Fields

Field

Bit

Description

Reserved

31:2

RsvdZ (Reserved; software must write 0)

Inference_complete

1

Indicates that an inference request has completed

Error

0

Indicates that an error condition has been triggered

Table 12.  Interrupt Mask Register (IMR) Fields

Field

Bit

Description

Reserved

31:2

RsvdZ (Reserved; software must write 0)

Inference_complete_mask

1

Set to one to enable interrupt generation on inference completion

Error_mask

0

Set to one to enable interrupt generation on error condition