Intel® FPGA AI Suite: IP Reference Manual

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ID 768974
Date 7/03/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite IP Reference Manual 2. About the Intel® FPGA AI Suite IP 3. Intel® FPGA AI Suite IP Generation Utility 4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. Intel® FPGA AI Suite IP Reference Manual Archives B. Intel® FPGA AI Suite IP Reference Manual Document Revision History
2. About the Intel® FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Intel® FPGA AI Suite Layer / Primitive Ranges 2.4. Intel® FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. Intel® FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter group: Global Parameters 2.4.2.2. Parameter group: activation 2.4.2.3. Parameter group: pe_array 2.4.2.4. Parameter group: pool 2.4.2.5. Module: softmax 2.4.2.6. Parameter group: dma 2.4.2.7. Parameter group: xbar 2.4.2.8. Parameter group: filter_scratchpad 2.4.2.9. Parameter group: config_network
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping
3. Intel® FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers
1. Intel® FPGA AI Suite IP Reference Manual
2. About the Intel® FPGA AI Suite IP
3. Intel® FPGA AI Suite IP Generation Utility
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. Intel® FPGA AI Suite IP Reference Manual Archives
B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

4.3. Running the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility

Before you run the Intel® FPGA AI Suite AOT splitter utility, you must have the following files ready:
  • A model compiled by the dla_compiler command. The model must target the HETERO:FPGA format and the output format must be open_vino_hetero.
    For example, the following command compiles a model that targets a board with an Intel Agilex® 7 device to a file called RN50_Performance_b1.bin: 
    cd $COREDLA_ROOT/demo/models/public/resnet-50-tf/FP32
dla_compiler \
  --march $COREDLA_ROOT/example_architectures/AGX7_Performance.arch \
  --network-file ./resnet-50-tf.xml \
  --foutput-format=open_vino_hetero \
  --o $COREDLA_ROOT/demo/RN50_Performance_b1.bin \
  --b=1 \
  --fanalyze-performance
  • The input or inputs for model inference.

The AOT splitter utility outputs the artifacts to the current working directory. The command line options must have a compiled model, model inputs, and a path to the splitter utility plugins XML file.

To run the AOT splitter utility:

  1. Change directories to where you want the output files from the AOT splitter utility to go.
  2. Run the splitter utility command as follows: 
    $COREDLA_ROOT/runtime/build_Release/dla_aot_splitter/dla_aot_splitter \
  -cm <full_path_to_compiled_model_file> \
  -i < XXX-delimited list of inference input files> \
  -plugins_xml_file <full_path_to_plugins_aot_splitter.xml> \
  [-bgr]

    The optional -bgr command option tells the AOT splitter to reverse the R, G, and B input channels for images before the channels are passed to the model.

    For example: 
    runtime/build_Release/dla_aot_splitter/dla_aot_splitter \
  -cm $COREDLA_ROOT/demo/RN50_Performance_b1.bin \
  -i $COREDLA_ROOT/demo/sample_images/val_00000000.bmp \
  -plugins_xml_file \
   runtime/dla_aot_splitter/dla_aot_splitter_plugin/plugins_aot_splitter.xml
  -bgr
Running the splitter generates the following files:
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