Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 7/03/2023
Public

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Document Table of Contents

2.5.1. Clock and Reset

Table 4.  Clocks

Name

Description

dla_clk

Clock used by internal processing logic

ddr_clk

Clock used by DDR memory and CSR interfaces

irq_clk

Clock used for interrupt request (IRQ) interface

Table 5.  Resets

Name

Description

dla_resetn

Global asynchronous reset

This reset must be held for at least three cycles of the slowest of the clocks listed in the Clocks table.

The IP becomes responsive sometime after the reset is released, but not immediately due to an internal reset cycle in the Intel® FPGA AI Suite IP.