FPGA AI Suite: Getting Started Guide

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ID 768970
Date 12/16/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Getting Started Guide 2. FPGA AI Suite Components 3. FPGA AI Suite Installation Overview 4. Installing the FPGA AI Suite Compiler and IP Generation Tools 5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites 6. FPGA AI Suite Quick Start Tutorial 7. Running the Hostless DDR-Free Design Example A. FPGA AI Suite Getting Started Guide Archives B. FPGA AI Suite Getting Started Guide Document Revision History
3. FPGA AI Suite Installation Overview x
3.1. FPGA AI Suite Directory Structure
4. Installing the FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the FPGA AI Suite with System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your FPGA AI Suite Installation
4.3. Installing the FPGA AI Suite with System Package Management Tools x
4.3.1. Installing the FPGA AI Suite Into an Alternative Location
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Agilex™ 7 Devices
6. FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics 6.13. Performing Inference Without an FPGA Board
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. FPGA AI Suite Getting Started Guide
2. FPGA AI Suite Components
3. FPGA AI Suite Installation Overview
4. Installing the FPGA AI Suite Compiler and IP Generation Tools
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites
6. FPGA AI Suite Quick Start Tutorial
7. Running the Hostless DDR-Free Design Example
A. FPGA AI Suite Getting Started Guide Archives
B. FPGA AI Suite Getting Started Guide Document Revision History

B. FPGA AI Suite Getting Started Guide Document Revision History

Document Version FPGA AI SuiteVersion Changes
2024.12.16 2024.3
  • Updated "Installing Quartus® Prime Pro Edition Software" to update the Quartus® Prime Pro Edition version required by the various FPGA boards supported by the FPGA AI Suite design examples.
2024.11.25 2024.3
  • Added description of the JTAG design example for Agilex™ 5 E-Series devices to " FPGA AI Suite Components".
2024.09.06 2024.2
  • Replaced occurrences of "memoryless" with "DDR-free".
  • Replaced occurrences of "software reference model" with "software emulation model".
2024.07.31 2024.2
  • Added "Running the Hostless Memoryless Design Example".
  • Added "Performing Inference Without an FPGA Board".
  • Updated supported OpenVINO™ version to 2023.3 LTS.
  • Revised "Setting Required Environment Variables".
  • Removed references to Intel® PAC with Arria® 10 GX FPGA.

    This card is no longer supported by FPGA AI Suite.

  • Removed references to Ubuntu 18.

    This operating system is no longer supported by FPGA AI Suite.

  • Replaced references to the -plugins_xml_file option with the -plugins option. The -plugins_xml_file option is deprecated and will be removed in a future release.
2024.03.29 2024.1
  • Added support for Ubuntu 22.04.
2024.02.12 2023.3.1
  • Updated for additional Agilex™ 7 support.
2024.02.02 2023.3
  • Corrected OpenVINO™ version in graphic in "FPGA AI Suite Installation Overview".
2023.12.01 2023.3
  • Added instructions for a WSL 2 environment to "Building an FPGA Bitstream for the PCIe Example Design".
2023.09.06 2023.2.1
  • Updated supported OpenVINO™ version to 2022.3.1 LTS.
  • Updated installation instructions for Ubuntu 18 operating systems.
2023.07.17 2023.2
  • Corrected instructions in "Installing OpenVINO™ Toolkit".
2023.07.03 2023.2
  • Added "Installing FPGA AI Suite on Windows* Subsystem for Linux".
  • Revised " OpenVINO™ Toolkit" for OpenVINO™ 2022.3 LTS.
  • Renamed "Installing the FPGA AI Suite " to " FPGA AI Suite Installation Overview" to better reflect the contents of that section.
  • Updated supported OpenVINO™ version to 2022.3 LTS.
  • Updated OpenVINO™ installation paths to /opt/intel/openvino_2023.
  • Updated FPGA AI Suite installation paths to /opt/intel/fpga_ai_suite_2023.2.
  • Changed occurrences of tools/downloader/downloader.py to omz_downloader.
  • Changed occurrences of tools/downloader/converter.py to omz_converter.
2023.04.05 2023.1
  • Added "Performing Inference on the i3d Graph".
  • Renamed thedlac command. The FPGA AI Suite compiler command is now dla_compiler.
  • Updated the Intel® Agilex™ product family name to "Intel Agilex® 7."
2022.12.23 2022.2
  • Update for the Debian package-based install.
  • Add walk-through for validating a YOLOv3 model.
  • Update to account for the new Terasic DE10-Agilex BSP ZIP file.
  • Renamed dla_create_and_build_pcie_ed.py to dla_build_example_design.py

2022.04.27

2022.1
  • Minor fixes to some file names, including one for the running inference in the AOT flow on the FPGA.

2022.04.12

2022.1
  • Notes on installing CMake for CentOS 7.
  • Clarifications to the Model Zoo and Model Optimizer install instructions.

2022.04.08

2022.1
  • Extensively revised installation instructions.
  • Added installation information for the PCI-based design examples.
  • Enhanced details for Intel Agilex devices.
  • Added a quick-start tutorial.
  • Removed supplementary performance details.

2021.09.10

2021.2
  • Added information for initial Intel Agilex device family support.

2021.04.30

2021.1
  • Expanded list of tasks performed by the Intel FPGA AI Suite Compiler.
  • Distinguished more clearly between requirements for the IP and requirements for the Example Designs.

2020.12.04

2020.2
  • Renamed the script that sets the Intel FPGA AI Suite environment variables to init_env.sh. It was called coredla_developer_init_env.sh in earlier releases.

2020.10.30

2020.1
  • Initial release.
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