FPGA AI Suite: Getting Started Guide

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ID 768970
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Getting Started Guide 2. FPGA AI Suite Components 3. FPGA AI Suite Installation Overview 4. Installing the FPGA AI Suite Compiler and IP Generation Tools 5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites 6. FPGA AI Suite Quick Start Tutorial 7. Running the Hostless DDR-Free Design Example A. FPGA AI Suite Getting Started Guide Archives B. FPGA AI Suite Getting Started Guide Document Revision History
3. FPGA AI Suite Installation Overview x
3.1. FPGA AI Suite Directory Structure
4. Installing the FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the FPGA AI Suite with System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your FPGA AI Suite Installation
4.3. Installing the FPGA AI Suite with System Package Management Tools x
4.3.1. Installing the FPGA AI Suite Into an Alternative Location
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Agilex™ 7 Devices
6. FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics 6.13. Performing Inference Without an FPGA Board
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. FPGA AI Suite Getting Started Guide
2. FPGA AI Suite Components
3. FPGA AI Suite Installation Overview
4. Installing the FPGA AI Suite Compiler and IP Generation Tools
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites
6. FPGA AI Suite Quick Start Tutorial
7. Running the Hostless DDR-Free Design Example
A. FPGA AI Suite Getting Started Guide Archives
B. FPGA AI Suite Getting Started Guide Document Revision History

2. FPGA AI Suite Components

The FPGA AI Suite consists of several components to help you enable AI on your Intel FPGAs.

The FPGA AI Suite consists of the following components:

  • Compiler (dla_compiler command)
    The FPGA AI Suite compiler is a multipurpose tool that you can use for the following tasks with the FPGA AI Suite:
    • Generate architectures

      Use the compiler to generate an IP parameterization that is optimized for a given machine learning (ML) model or set of models, while attempting to fit the FPGA AI Suite IP block into a given resource footprint.

    • Estimate IP performance

      Use the compiler to get an estimate of the performance of the AI IP block for a given parameterization.

    • Estimate IP FPGA resource consumption

      Use the compiler to get an estimate of the FPGA resources (ALMs, M20k blocks, and DSPs) required for a given IP parameterization.

    • Create an ahead-of-time compiled graph

      Create a compiled version of an ML model that includes the instructions necessary to control the IP on the FPGA. The compiled binary includes both the instructions to control the IP during inference and the model weights. This compiled model is suitable for use by the Example Designs or in a production deployment.

    An OpenVINO™ plugin is distributed with the compiler that allows the PCIe Example Design to access the compiler in a just-in-time fashion.

  • IP generation tool

The FPGA AI Suite IP generation tool customizes the FPGA AI Suite IP based on an input architecture file. The generated IP is placed into an IP library that you can import into an FPGA design with Platform Designer, use directly in a pure RTL design, or both.

  • Example designs
The following design examples show how you can use the FPGA AI Suite IP:
  • PCIe-based design example for Agilex™ 7 devices

    This design example targets the Terasic* DE10-Agilex Development Board (DE10-Agilex-B2E2). This example is distributed with the FPGA AI Suite.

    This example highlights how to instantiate the FPGA AI Suite IP and provides an example runtime that shows you how to control the FPGA AI Suite IP and pass the model configuration to the IP to program it and run inference on a neural network.

  • SoC design example for Arria® 10 devices

    This design example is based on the Arria® 10 SX SoC FPGA Development Kit (DK-SOC-10AS066S). This example is distributed with the FPGA AI Suite.

    This example demonstrates how to use the ARM* SoC as a host for the FPGA AI Suite, as well as how to perform inference in a streaming data flow.

  • SoC design example for Agilex™ 7 devices

    This design example is based on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (DK-SI-AGI027FC). This example is distributed with the FPGA AI Suite.

    This example demonstrates how to use the ARM* SoC as a host for the FPGA AI Suite, as well as how to perform inference in a streaming data flow.

  • Streaming hostless design examples for Agilex™ 7 devices

    This design example is based on the Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES). This example is distributed with the FPGA AI Suite.

    This example demonstrates how to create an instance of the FPGA AI Suite IP that does not have any dependency on external memory. Input (output) data are streamed into (out of) the IP. The IP is manually controlled by using the Quartus® Prime System Console.

  • JTAG design example for Agilex™ 5 E-Series devices

    This design example is based on the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (DK-A5E065BB32AES1). This example is distributed with the FPGA AI Suite.

    This example demonstrates how to instantiate one instance of the FPGA AI Suite IP on an Agilex™ 5 E-Series device. It places configurations and data on external DDR memory and allows an external host to interact with the memory and FPGA AI Suite IP via JTAG.

  • ARM-based design example

    This design example is based on using an Arria® 10 SoC FPGA.

    This example highlights how to use the FPGA AI Suite IP in a fully embedded FPGA design, with direct camera input and a video IP pipeline connected to the FPGA AI Suite IP.

    This example design is available separately and is not provided with the FPGA AI Suite.

The following diagram illustrates the connection between two primary components of the FPGA AI Suite – the compiler and the IP:
Figure 1. Connection Between FPGA AI Suite Compiler and FPGA AI Suite IP


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