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1. FPGA AI Suite Getting Started Guide
2. FPGA AI Suite Components
3. FPGA AI Suite Installation Overview
4. Installing the FPGA AI Suite Compiler and IP Generation Tools
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites
6. FPGA AI Suite Quick Start Tutorial
7. Running the Hostless DDR-Free Design Example
A. FPGA AI Suite Getting Started Guide Archives
B. FPGA AI Suite Getting Started Guide Document Revision History
4.1. Supported FPGA Families
4.2. Operating System Prerequisites
4.3. Installing the FPGA AI Suite with System Package Management Tools
4.4. Installing OpenVINO™ Toolkit
4.5. Installing Quartus® Prime Pro Edition Software
4.6. Setting Required Environment Variables
4.7. Installing Intel® Threading Building Blocks (TBB)
4.8. Finalizing Your FPGA AI Suite Installation
6.1. Creating a Working Directory
6.2. Preparing OpenVINO™ Model Zoo
6.3. Preparing a Model
6.4. Running the Graph Compiler
6.5. Preparing an Image Set
6.6. Programming the FPGA Device
6.7. Performing Inference on the PCIe-Based Example Design
6.8. Building an FPGA Bitstream for the PCIe Example Design
6.9. Building the Example FPGA Bitstreams
6.10. Preparing a ResNet50 v1 Model
6.11. Performing Inference on the Inflated 3D (I3D) Graph
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.13. Performing Inference Without an FPGA Board
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6. FPGA AI Suite Quick Start Tutorial
The examples in this section assume that you have installed the FPGA AI Suite according to the instructions in Installing the FPGA AI Suite Compiler and IP Generation Tools.
Ensure that you the required environment variables set. For details, refer to Setting Required Environment Variables.
A quick command to check that the FPGA AI Suite installation was successful is as follows:
dla_compiler --fanalyze-area --march $COREDLA_ROOT/*/AGX7_Generic.arch
Section Content
Creating a Working Directory
Preparing OpenVINO Model Zoo
Preparing a Model
Running the Graph Compiler
Preparing an Image Set
Programming the FPGA Device
Performing Inference on the PCIe-Based Example Design
Building an FPGA Bitstream for the PCIe Example Design
Building the Example FPGA Bitstreams
Preparing a ResNet50 v1 Model
Performing Inference on the Inflated 3D (I3D) Graph
Performing Inference on YOLOv3 and Calculating Accuracy Metrics
Performing Inference Without an FPGA Board