FPGA AI Suite: Getting Started Guide

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ID 768970
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Getting Started Guide 2. FPGA AI Suite Components 3. FPGA AI Suite Installation Overview 4. Installing the FPGA AI Suite Compiler and IP Generation Tools 5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites 6. FPGA AI Suite Quick Start Tutorial 7. Running the Hostless DDR-Free Design Example A. FPGA AI Suite Getting Started Guide Archives B. FPGA AI Suite Getting Started Guide Document Revision History
3. FPGA AI Suite Installation Overview x
3.1. FPGA AI Suite Directory Structure
4. Installing the FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the FPGA AI Suite with System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your FPGA AI Suite Installation
4.3. Installing the FPGA AI Suite with System Package Management Tools x
4.3.1. Installing the FPGA AI Suite Into an Alternative Location
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Agilex™ 7 Devices Ubuntu* Kernel Prerequisites Terasic Kernel Driver Software Prerequisites Terasic Driver Installation Ubuntu* Kernel Update Requirements Bitstream Generation Requirements Reboot Requirements
6. FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics 6.13. Performing Inference Without an FPGA Board
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. FPGA AI Suite Getting Started Guide
2. FPGA AI Suite Components
3. FPGA AI Suite Installation Overview
4. Installing the FPGA AI Suite Compiler and IP Generation Tools
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites
6. FPGA AI Suite Quick Start Tutorial
7. Running the Hostless DDR-Free Design Example
A. FPGA AI Suite Getting Started Guide Archives
B. FPGA AI Suite Getting Started Guide Document Revision History

5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Agilex™ 7 Devices

The kernel driver for the Terasic BSP must be installed according to instructions provided by Terasic. Follow the instructions that follow, or contact your Terasic representative for additional details.

Important: If you follow the Terasic instructions, the Terasic instructions (on page 35) say to override the $LD_LIBRARY_PATH environment variable. Do not override the environment variable. Append paths to the $LD_LIBRARY_PATH environment variable instead.

A copy of the verified Terasic kernel driver is distributed as a separate file: DE10_Agilex_revC_linux_BSP_21.2.zip. Obtain this file from your Terasic representative.

Ubuntu* Kernel Prerequisites

The kernel driver is tested on the Ubuntu* 20.04.5 LTS distribution with kernel version 5.15.0. You can confirm the kernel version of your Ubuntu system with the following command: 
uname -r

Terasic Kernel Driver Software Prerequisites

To install the Terasic kernel driver, install the following software dependencies:

After you have installed the Quartus Programmer, set up the required environment variable using the following command: 
export PATH="$PATH:"<path to Quartus Programmer installation folder>/qprogrammer/quartus/bin

Your system must recognize the Intel® FPGA Download Cable II to install the Terasic kernel driver and program your board.

To verify the connection of the Intel® FPGA Download Cable II, issue the jtagconfig command. You should see the DE10-Agilex device listed. An example of the expected output is as follows: 
$ jtagconfig
1) DE10-Agilex [1-11.1]
C24A0DD   AGFB014R24(A|B)
The list index number ("1" in the example) is also the cable number, which can be used to reprogram the board in Terasic Driver Installation.

Terasic Driver Installation

After you meet the Terasic kernel driver software prerequisites, complete the following steps:
  1. Set up the environment with the following command:
    source <full path to opencl rte installation>/init_opencl.sh
  2. Unzip the board support package in the current directory and set up the following environment variables (The value $PWD in the commands that follow must correspond to the directory in which the BSP packages was unzipped):
    tmp1=$PWD/DE10_Agilex_revC_linux_BSP_21.2/de10_agilex
export AOCL_BOARD_PACKAGE_ROOT=$tmp1
tmp1=$ALTERAOCLSDKROOT/host/linux64/lib
tmp2=$AOCL_BOARD_PACKAGE_ROOT/linux64/lib
export LD_LIBRARY_PATH=$tmp1:$tmp2:$LD_LIBRARY_PATH
  3. Install the driver with the following command:
    aocl install
  4. Rescan the PCIe bus or reboot the system to program the board. To verify that the driver bonds to the card, program the testing bitstream to the board with the following command:
    quartus_pgm -c <cable_number> -m jtag \
  -o "p;$AOCL_BOARD_PACKAGE_ROOT/bringup/B2E2_8GBx4/top.sof"
  5. Perform a soft reboot of your host system for the system to recognize the Terasic* DE10-Agilex Development Board: 
    reboot
    You can verify that the board is recognized by the host system with the following command: 
    lspci | grep Altera

    If you do not see the board information when scanning the PCIe bus, try rebooting your system or reinstalling the board. In some cases, you might need to move the card to a different PCIe slot.

For more details and information about the Terasic kernel driver, refer to the Terasic OpenCL BSP Guide, DE10-Agilex_OpenCL_21.2.pdf, in the kernel driver package.

Ubuntu* Kernel Update Requirements

If you update your Ubuntu* kernel, you must reinstall the Terasic kernel driver.

Bitstream Generation Requirements

If you plan to use only the precompiled bitstreams supplied with the FPGA AI Suite, then no further steps are required.

If you plan to generate bitstreams corresponding to custom FPGA AI Suite IP architectures for the PCIe-based example design for Agilex™ 7 devices, then you must install Quartus® Prime Pro Edition Version 24.2 and setup your PATH environment variable.

For Quartus® Prime Pro Edition Version 24.2 prerequisites and installation instructions, refer to Intel FPGA Software Installation and Licensing .

Download the Quartus® Prime Pro Edition software from the following URL: https://www.intel.com/content/www/us/en/software-kit/current/657471.html

Bitstream generation works with Quartus® Prime Pro Edition Version 24.2, even though the Terasic driver requires Intel® FPGA RTE for OpenCL™ Version 21.2.

You must also add the Platform Designer command (qsys) to your PATH environment variable. Add the following commands to your .bashrc file, and adjust the paths depending on your installation locations, if needed: 
export PATH="$PATH:"~/intelFPGA_pro/quartus_24.2/qsys/bin/
export PATH="$PATH:"~/intelFPGA_pro/quartus_24.2/quartus/bin/

Reboot Requirements

Any time that you reboot your system after powering down, you must reprogram the board with the following command: 
quartus_pgm -c <cable_number> -m jtag \
     –o "p;$AOCL_BOARD_PACKAGE_ROOT/bringup/B2E2_8GBx4/top.sof"

After you successfully install the board, continue by installing the compiler and IP generation tool as described in Installing the FPGA AI Suite Compiler and IP Generation Tools.

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