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1. FPGA AI Suite Getting Started Guide
2. FPGA AI Suite Components
3. FPGA AI Suite Installation Overview
4. Installing the FPGA AI Suite Compiler and IP Generation Tools
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites
6. FPGA AI Suite Quick Start Tutorial
7. Running the Hostless Memoryless Design Example
A. FPGA AI Suite Getting Started Guide Archives
B. FPGA AI Suite Getting Started Guide Document Revision History
4.1. Supported FPGA Families
4.2. Operating System Prerequisites
4.3. Installing the FPGA AI Suite with System Package Management Tools
4.4. Installing OpenVINO™ Toolkit
4.5. Installing Quartus® Prime Pro Edition Software
4.6. Setting Required Environment Variables
4.7. Installing Intel® Threading Building Blocks (TBB)
4.8. Finalizing Your FPGA AI Suite Installation
6.1. Creating a Working Directory
6.2. Preparing OpenVINO™ Model Zoo
6.3. Preparing a Model
6.4. Running the Graph Compiler
6.5. Preparing an Image Set
6.6. Programming the FPGA Device
6.7. Performing Inference on the PCIe-Based Example Design
6.8. Building an FPGA Bitstream for the PCIe Example Design
6.9. Building the Example FPGA Bitstreams
6.10. Preparing a ResNet50 v1 Model
6.11. Performing Inference on the Inflated 3D (I3D) Graph
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.13. Performing Inference Without an FPGA Board
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6.13. Performing Inference Without an FPGA Board
The software reference model is a C++ software model of the FPGA AI Suite IP. It is not cycle-accurate, but it can be described as "cycle-similar". The reference model models relatively low-level transactions and, in some cases, models processing delays of modules.
To use the software reference model:
- Build the runtime with the following commands:
cd $COREDLA_WORK/runtime rm -rf build_Release ./build_runtime.sh -target_reference
- Run inference with the -niter=1 and -nireq=1 options (because the software model is reasonably slow) with the following commands:
modeldir=$COREDLA_WORK/demo/models/public imagedir=$COREDLA_WORK/demo/sample_images curarch=$COREDLA_ROOT/example_architectures/AGX7_Performance.arch gnd=$imagedir/TF_ground_truth.txt ./dla_benchmark \ -b 1 `# Run only a single image` \ -niter 1 `# Run only a single image` \ -nireq 1 `# Running reference: so -nireq=1` \ -m $modeldir/resnet-50-tf/FP32/resnet-50-tf.xml \ `# Same as when running on hardware - specify the graph` \ -d HETERO:FPGA,CPU \ `# Same as when running on hardware - \ use FPGA if possible, fallback to CPU` \ -i $imagedir `# Same as when running on hardware - specify image directory` \ -arch_file $curarch `# Same as when running on hardware - specify .arch file` \ -dump_output `# Dump output result.txt file` \ -plugins reference `# Use the software reference` \ -groundtruth_loc $gnd `# Location of the ground truth file for $imagedir`