FPGA AI Suite: Getting Started Guide

ID 768970
Date 9/06/2024
Public
Document Table of Contents

6.4. Running the Graph Compiler

The FPGA AI Suite compiler (dla_compiler tool) can estimate the performance of a graph and IP architecture combination. The tool can also produce a compiled network that the runtime uses in AOT (ahead-of-time) mode to control inference on the IP.

The following commands generate an AOT file for Agilex™ 7 devices:
cd $COREDLA_WORK/demo/models/public/resnet-50-tf/FP32
dla_compiler \
            --march $COREDLA_ROOT/example_architectures/AGX7_Performance.arch \
            --network-file ./resnet-50-tf.xml \
            --foutput-format=open_vino_hetero \
            --o $COREDLA_WORK/demo/RN50_Performance_b1.bin \
            --batch-size=1 \
            --fanalyze-performance
         
These command specify the following input files:
  • The .arch file specifies the configuration of the IP architecture (configuration parameters such as large, small, and which activations to use).
  • The .xml file (along with the .bin) describes the network.
  • The .bin file stores certain parameters along with the model weights.
The FPGA AI Suite compiler uses these files to analyze the performance estimate.

The output file RN50_Performance_b1.bin is the compiled network and contains the instructions and graph weights necessary to control the FPGA AI Suite IP on the FPGA device. This output file is specific to the .arch file and the graph .xml file.

The compiler dot graph shows which layers run on the FPGA and which layers run on the CPU. Using the Graphviz package, the dot file format can be converted into an SVG graphics file named ResNet-50.svg that shows each layer. You can view SVG graphics in most web browsers. Use the following command to convert the dot graph file into an SVG file:
dot -Tsvg hetero_subgraphs_resnet-50-tf.dot -o ResNet-50.svg