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Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
3.4.1. General NoC IP Connectivity Guidelines
3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
3.4.4. Connectivity Guidelines: NoC Clock Control
3.4.5. Connectivity Guidelines: NoC Initiators for HPS
3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces
7.1.2.2. NoC Initiator AXI4 User Interface Signals
7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals
7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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2.5. NoC Protocol Support
The hard memory NoC in Agilex™ 7 M-Series FPGAs supports the following transaction protocols:
- AMBA AXI4 protocol—used by the memory controller targets, fabric initiators, and the two HPS AXI4 initiators.
- AMBA AXI4 Lite protocol—used by targets handling sideband operation, the HPS AXI4 Lite initiator, and by fabric initiators to communicate with AXI4 Lite targets through the NoC SSM.