F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 7/08/2024
Public
Document Table of Contents

7.9. Reset Signals

The IP core has five reset inputs. These resets are asynchronous and are internally synchronized.
Table 22.   Reset Signals

Signal

Direction

Description

i_rst_n Input Active low reset asynchronous signal. Do not deassert until the o_rst_ack_n deasserts.
  • Resets the TX interface, including the TX PCS.
  • Resets the RX interface, including the RX PCS.
  • Resets the TX PMA and TX EMIB.
  • Resets the RX PMA and RX EMIB.

This reset leads to the assertion of the o_rst_ack_n output signals.

o_rst_ack_n Output Active low asynchronous acknowledgement signal for i_rst_n.

Do not deassert i_rst_n until the o_rst_ack_n asserts.

i_tx_rst_n Input Active low reset asynchronous signal. Resets the TX datapath, including the TX PCS, TX MAC, TX PMA, and TX EMIB. Do not deassert until the o_tx_rst_ack_n asserts.
o_tx_rst_ack_n Output Active low asynchronous acknowledgement signal for the i_tx_rst_n. Do not deassert i_tx_rst_n until the o_tx_rst_ack_n asserts.
i_rx_rst_n Input

Active low hard reset signal. Resets the RX datapath, including the RX PCS, RX MAC, RX PMA, and RX EMIB. Do not deassert until the o_rx_rst_ack_n asserts.

o_rx_rst_ack_n Output Active low asynchronous acknowledgement signal for the i_rx_rst_n. Do not deassert i_rx_rst_n until the o_rx_rst_ack_n asserts.
reconfig_reset Input Active high reconfiguration reset signal. Reset the entire transceiver and ethernet reconfiguration clock domain, including the soft registers (CSRs).

You must assert this reset after power-on or during the configuration. The reconfig_clk must be stable before deasserting this reset.

csr_rst_n Input

Active low hard reset. Resets the MAC control, status, and statistics registers.