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1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
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4.2. Analog Parameter Tab Options
You can set the analog parameters in the Analog Parameter tab in the parameter editor. If you do not set the analog parameters, the Quartus® Prime Pro Edition automatically selects a valid value that may not be appropriate for your board. The Quartus® Prime Pro Edition would also generate a critical warning to remind you to set the parameters in your design .qsf file.
Note: The settings in the .qsf file takes precedence over the settings in the Analog Parameter tab in the parameter editor. You must remove any settings in the .qsf file before setting the parameter editor.
For more details on analog parameter options, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
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