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1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
Visible to Intel only — GUID: quv1649917101351
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2.4. Performance and Resource Utilization
The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. The timing margin for this IP core is a minimum of 15%.
IP Core Settings | ALMs |
Dedicated Logic Registers |
Block Memory Bits |
---|---|---|---|
RS-FEC disabled | 9749 | 17937 | 177728 |
RS-FEC enabled | 9846 |
IP Core Settings |
Latency (ns) |
---|---|
RS-FEC disabled | 255 |
RS-FEC enabled | 685 |