AN 973: Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging

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ID 733436
Date 6/23/2022
Public
Document Table of Contents
Document Table of Contents x
1. Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging Design Example Overview 2. Downloading and Installing the Design Example 3. Model Description 4. FPGA Resource Use Comparison 5. Locating Top-level VHDL Wrapper 6. Generating HDL Code with MATLAB and HDL Coder 7. Simulink Simulation Results 8. Document Revision History for AN 973: Three-phase Boost Bidirectional AC/DC Converter for EV Charging
2. Downloading and Installing the Design Example x
2.1. Software Requirements 2.2. Hardware Requirements 2.3. Downloading and Installing the Design
3. Model Description x
3.1. Simscape* Model 3.2. Simulink* Model 3.3. HDL Inputs, Outputs, and Parameters
3.2. Simulink* Model x
3.2.1. Controller Block 3.2.2. Power Electronics Block Model 3.2.3. Source Voltage Generator Block
3.2.1. Controller Block x
3.2.1.1. Pulse Width Modulation (PWM) Controller 3.2.1.2. Phase-locked Loop (PLL) 3.2.1.3. Sampling Circuit 3.2.1.4. Clarke and Park Transforms
3.2.2. Power Electronics Block Model x
3.2.2.1. Six-switch Power Converter 3.2.2.2. Inductors 3.2.2.3. Output Capacitor
6. Generating HDL Code with MATLAB and HDL Coder x
6.1. Generating HDL and QPF Using MATLAB Scripts 6.2. Generating HDL and QPF Using MATLAB GUI Tools
1. Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging Design Example Overview
2. Downloading and Installing the Design Example
3. Model Description
4. FPGA Resource Use Comparison
5. Locating Top-level VHDL Wrapper
6. Generating HDL Code with MATLAB and HDL Coder
7. Simulink Simulation Results
8. Document Revision History for AN 973: Three-phase Boost Bidirectional AC/DC Converter for EV Charging

6.2. Generating HDL and QPF Using MATLAB GUI Tools

This section provides instructions to generate an Intel® Quartus® Prime software project and VHDL code for the fixed-point model described in the bidir_rectifier.slx file.

Follow these steps:

  1. Launch the MATLAB model in the matlab/Simulink/bidir_rectifier.slx directory. The MATLAB and Simulink window launches.
  2. In the MATLAB interface, select the parameters.m file and click Run. This sets some necessary variables to synthesize the model.
    Figure 20. Setting Up Model Variables
  3. Launch the Simulink window where you can see the model that is synthesized and used to generate an Intel® Quartus® Prime software project and VHDL code (bidir_rectifier_fixed).
  4. In the Simulink window, navigate to the HDL CODE tab and click Workflow Advisor. A warning of a missing ./top.vhd appears. Ignore the warning.
    Figure 21. Workflow Advisor and Simulink GUI
  5. Expand the HDL Workflow Advisor tasks menu in the left-hand pane.
  6. Select 1.1 Set Target Device and Synthesis Tool to configure the target FPGA device and perform one of the following:
    • For Intel® MAX® 10 FPGA Development Kit: Select the value for Family as MAX 10 and Device as 10M50DAF484C6GES.
    • For Cyclone® V SoC Development Kit: Select the value for Family as Cyclone V and Device as 5CSXFC6D6F31C6.
  7. Change the Project folder to a desired project location and name.
  8. In the left-hand pane, select 4.1 Create Project.
    Figure 22. Running Tasks in HDL Workflow Advisor
  9. For Additional source files, select one of the following:
    • For Intel® MAX® 10 FPGA Development Kit: <local_path>/M10/top.vhd
    • For Cyclone® V SoC Development Kit: <local_path>/C5/top.vhd
  10. For Additional project creation Tcl files, select one of the following:
    • For Intel® MAX® 10 FPGA Development Kit: <local>/matlab/Simulink/m10/add_to_project.tcl
    • For Cyclone® V SoC Development Kit: <local>/matlab/Simulink/c5/add_to_project.tcl
  11. Run tasks 1, 2, 3, and 4.1 by clicking Run This Task.
  12. Navigate to the project folder that you selected in step 7. The newly created Intel® Quartus® Prime software project is located in the quartus_prj directory and the generated VHDL code for the Simulink model is located in the hdlsrc directory.
  13. Navigate to the quartus_prj directory and open the bidir_rectifier_fixed_quartus.qpf file with the Intel® Quartus® Prime software.
  14. Compile the design, generate a SOF file, and program your board as described in Downloading and Installing the Design. Use Signal Tap logic analyzer to view the waveforms created by the generated VHDL code programmed in your board.
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