AN 973: Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging

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ID 733436
Date 6/23/2022
Public
Document Table of Contents
Document Table of Contents x
1. Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging Design Example Overview 2. Downloading and Installing the Design Example 3. Model Description 4. FPGA Resource Use Comparison 5. Locating Top-level VHDL Wrapper 6. Generating HDL Code with MATLAB and HDL Coder 7. Simulink Simulation Results 8. Document Revision History for AN 973: Three-phase Boost Bidirectional AC/DC Converter for EV Charging
2. Downloading and Installing the Design Example x
2.1. Software Requirements 2.2. Hardware Requirements 2.3. Downloading and Installing the Design
3. Model Description x
3.1. Simscape* Model 3.2. Simulink* Model 3.3. HDL Inputs, Outputs, and Parameters
3.2. Simulink* Model x
3.2.1. Controller Block 3.2.2. Power Electronics Block Model 3.2.3. Source Voltage Generator Block
3.2.1. Controller Block x
3.2.1.1. Pulse Width Modulation (PWM) Controller 3.2.1.2. Phase-locked Loop (PLL) 3.2.1.3. Sampling Circuit 3.2.1.4. Clarke and Park Transforms
3.2.2. Power Electronics Block Model x
3.2.2.1. Six-switch Power Converter 3.2.2.2. Inductors 3.2.2.3. Output Capacitor
6. Generating HDL Code with MATLAB and HDL Coder x
6.1. Generating HDL and QPF Using MATLAB Scripts 6.2. Generating HDL and QPF Using MATLAB GUI Tools
1. Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging Design Example Overview
2. Downloading and Installing the Design Example
3. Model Description
4. FPGA Resource Use Comparison
5. Locating Top-level VHDL Wrapper
6. Generating HDL Code with MATLAB and HDL Coder
7. Simulink Simulation Results
8. Document Revision History for AN 973: Three-phase Boost Bidirectional AC/DC Converter for EV Charging

4. FPGA Resource Use Comparison

The following tables show FPGA resource use for the fixed-point Simulink* implementation of the Three-phase Boost Bidirectional AC/DC Converter for EV Charging design example based on Cyclone® V SoC FPGA Development Kit and Intel® MAX® 10 FPGA Development Kit after Intel® Quartus® Prime software compilation. Tables show the main entities' resource utilization and the total utilization of the FPGA.
Table 5.  FPGA Resource Use for Intel® MAX® 10 FPGA Development Kit
Entity LEs Regs Mem. Bits M9Ks DSPs DSP 9x9 DSP 18x18
Bidir_rectifier_fixed (from MATLAB) 6983 3530 35328 6 137 5 66
Power electronics (model) 1923 622 0 0 27 3 12
Controller 4542 2559 11776 2 98 2 48
Voltage Generator 530 349 23552 4 12 0 6
Signal Tap Block 4214 3808 209920 23 0 0 0
Others 648 456 0 0 0 0 0
Total 11845 (24%) 7794 (15%) 245248 (15%) 29 (16%) 137 (48%) 5 (2%) 66 (46%)
Table 6.  FPGA Resource Use for Cyclone® V SoC FPGA Development Kit
Entity ALMs Registers Mem. Bits M10Ks DSP Blocks
Bidir_rectifier_fixed (from MATLAB) 1912 3651 35328 6 56
Power electronics (model) 590 674 0 0 13
Controller 1168 2618 11776 2 377
Voltage Generator 156 359 23552 4 6
Signal Tap 1124 3848 209920 21 0
Others 561 471 0 0 0
Total 3597 (9%) 7970 (10%) 245248 (4%) 27 (5%) 56 (50%)
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