Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 7/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project

Debug Configuration reuses the setting made in Run Configuration. If you have completed the setting, you can skip this subchapter.

You can download and run Nios® V processor software project on the targeted Intel FPGA using the Ashling* RiscFree* IDE for Intel® FPGAs. To run the project, follow these steps:

  1. Right-click the project folder (application or BSP) in the project explorer and select Debug As > Debug configurations.
  2. Select Ashling RISC-V Hardware Debugging > <Project Name>. Ensure the Project and C/C++ Application match with your project name and your project .elf file respectively.
  3. Under the Main tab, for C/C++ Application, browse to select the application build .elf file. For example: hello.elf.
    Figure 18. Debug Configurations for Nios® V Processor—Main Tab
  4. Under the Debugger tab, set these settings:
    • Debug probe: Agilex SI/SoC Dev Kit (Name of the FPGA board/development kit)
    • Transport type: JTAG
    • JTAG frequency: 16 MHz
    Figure 19. Debug Configurations for Nios® V Processor—Debugger Tab
  5. Click Auto-detect Scan Chain to automatically detect JTAG scan chain information of the target device. Select the options from Device/Tap selection and Core selection.
  6. Navigate to Startup tab, go to Load Image and Symbols, turn off Load Image.
    Figure 20. Disable Load Image
  7. Based on the OS you use, configure the OS Awareness settings as follows:
    • Intel HAL: No OS Awareness configuration is required.
    • Other OS: Under the OS Awareness tab, turn on Enable OS Aware Debugging, and select the OS version applicable to you as listed below:
      • OS: μC/OS-II and Version: 2.93.0
      • OS: FreeRTOS and Version: 10.5.0
      • OS: Zephyr and Version: 3.2.0
        Note: Nios® V processor does not support Linux OS.
      Figure 21. Enabling OS Aware Debugging in RISC-V Hardware Debugging
  8. Click Debug. RiscFree* IDE for Intel® FPGAs downloads the program to the target and you can find the console prints as shown in the following diagram.
    Figure 22. Console Prints after Debug Connection is Successful
    Currently, the program is running in debug mode. You can check the Debug tab on the left side of the RiscFree* IDE for Intel® FPGAs.
    Figure 23. Debug state - Running
    Note: Before you proceed to debug, make sure the debugger is in Suspended state. For more information on how to suspend the debugger, refer to GUI for Debugging.
    Figure 24. Debug state - Suspended
  9. Click Suspend icon in the Debug bar.

    To verify the boot copier has copied the application successfully, continue with the following steps:

  10. Go to Window > Show View > Memory Browser.
  11. Select Add Memory Monitor.
  12. Provide the memory address 0x0 and click OK.
    Figure 25. Memory Browser at Address 0x0
  13. Go to <Working directory>/software/app/build/Default folder.
  14. Open the hello.elf.objdump file.
  15. Search for Disassembly of section .entry.
  16. The disassembly shows that the information at starting address 0 is 0x3680006f, which is exactly the same as in the Memory Browser.
  17. You can continue to verify section .exceptions.
    Figure 26. Disassembly of an Application
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