Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

5.8.2. Debugging the Arm* HPS Linux Kernel

Refer to the following steps to debug the Arm* HPS Linux Kernel:
  1. Boot Linux* on the Agilex™ development board using a Linux kernel ready for debugging.
  2. Go to File > Import > C/C++ Executable then click Next.
    Figure 67. Selecting Import Wizard
  3. In the Import Executable window, click Browse… and select the vmlinux executable location on your computer. Click Next.
    Figure 68. Importing C/C++ Executable Files
  4. Use Linux Kernel Debug for New project name. Select Ashling Heterogeneous Multicore Hardware Debug for Create a Launch Configuration, then click Finish.
    Figure 69. Choosing Project
  5. The Debug Configurations window appears. Use the Auto-detect Scan Chain button, if you need to populate the device list in the Device tab in the launch configuration. Perform and repeat the following steps for all four Cortex-A53 cores.
    Figure 70. Creating, Managing, and Running Configuration
    1. For the Linux debug session, check all the cores that Linux is running on as shown below.
      Figure 71. Linux Cores
      Note: Altera recommends you specify a proper memory access attributes to avoid unwanted or illegal memory access during the debug session. For example, the memory access region configured for Agilex™ platform is: 
      set remotetimeout 10
set mem inaccessible-by-default on
mem 0xffff000000000000 0xffff0003ffffffff rw
mem 0xffff800000000000 0xffff802effffffff rw
      Ensure you select the default path and then select aarch64-none-linux-gnu-gdb as the GDB Executable name.
    2. Click Target Application tab. Click Add. The Browse Executable window appears. For Project, click Browse... and select the current project. For C/C++ Application, click Browse... and select vmlinux as the executable. Click OK.
      Figure 72. Browse Executable Window
    3. After adding the executable, ensure you turn off Load image as the image is already loaded to the target.
      Figure 73. Target Application Tab
    4. Click the Startup tab. Ensure the configuration is as shown below.
      Figure 74. Startup Tab
    5. Go to OS Awareness tab. Turn on the OS Aware Debugging checkbox and select appropriate Linux kernel version.
      Figure 75. OS Awareness Tab
  6. After you complete the configurations for all of the Cortex-A53 cores, click Apply then click Debug. The debugger connects to the Linux running on the board, then it stops the cores, and display the current code, as shown below.
    Figure 76. idle.c tab
  7. Go to Linux > Processes > List Running Processes, and then the debugger shows the processes.
    Figure 77. Linux Process
  8. Right-click a process in the list, then select the Watch option. The debugger opens the process in the Watch window. You can now inspect its properties.
    Figure 78. Inspecting the Process Properties

    The following figure shows an example of the Linux process properties.

    Figure 79. Process Properties
  9. Go to Linux > Modules > List Loaded Modules to show the list of modules. In the example below only one module was loaded:
    Figure 80. Linux Modules
  10. Right-click a module in the list, then select the Watch option. You can inspect the module properties as shown in the figure below:
    Figure 81. Module Properties
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