Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

2.2.1.6. Running the Project

You can run a Nios® V processor program using the RiscFree* IDE for Intel® FPGAs on Run Configurations, such as an Intel FPGA development board.

To run a software project, navigate to Run and click Run Configurations. This command conducts the following actions:

  • Creates an Ashling RISC-V Hardware Debugging.
  • Builds the project executable. If all target files are up to date, nothing is built.
  • Establishes communications with the target, and verifies that the FPGA is configured with the correct hardware design.
  • Downloads the Executable and Linking Format File (.elf) to the target memory
  • Starts execution at the .elf entry point.

To disconnect the terminal from the target, click the Terminate icon in the Console view. Terminating only disconnects the host from the target. The target processor continues executing the program.

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