Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

6.3. Nios® V Processor Example

The following is the example of running Ashling* GDBServer at port 54321 on Agilex™ 7 FPGA - Hello World Design on Nios® V/m Processor example design. 
$ jtagconfig.exe -d
1) AGF FPGA Development Kit on 10.107.209.7:3590 [3-1.1]
   (JTAG Server Version 22.1.0 Build 174 03/30/2022 SC Pro Edition)
  C341A0DD   AGFB014R24A(.|R1|R2)/.. (IR=10)
    Design hash    74DFB795DF11A555CEDF
    + Node 00486E00  Source/Probe #0
    + Node 08986E00  Nios V #0
    + Node 0C006E00  JTAG UART #0
  031830DD   10M16S(A|C|L) (IR=10)

  Captured DR after reset = (30D068376063061BB020D10DD) [98]
  Captured IR after reset = (006AAD55) [32]
  Captured Bypass after reset = (0A) [5]
  Captured Bypass chain = (00) [5]
  JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0
  JTAG clock speed 24 MHz

Refer to the following steps to debug the Nios® V processor application ELF in the GDB:

  1. On the first terminal or command prompt, start the Ashling* GDBServer. For the rest of the walkthrough, this terminal is called as Ashling* GDBServer.
    $ ash-riscv-gdb-server.exe --device C341A0DD \
--auto-detect true --probe-type usb-blaster-2 \
--core-number 0 --jtag-frequency auto-adjust \
--gdb-port 54321

Ashling GDB Server for RISC-V (ash-riscv-gdb-server).
v23.3.2, 01-Sep-2023, (c)Ashling Microsystems Ltd 2023.

Initializing connection ...
Checking for an active debug connection using the selected debug probe (SN: 16777217):
Connected to target device with IDCODE 0xc341a0dd using USB-Blaster-2 via JTAG at adaptive speed.
Info : Active Harts Detected : 1
Info : [0] System architecture : RV32
Info : [0] Number of hardware breakpoints available : 1 
Info : [0] Number of program buffers: 8
Info : [0] Number of data registers: 2
Info : [0] Memory access -> Program buffer
Info : [0] Memory access -> Abstract access memory
Info : [0] CSR & FP Register access -> Abstract commands

Waiting for debugger connection on port 54321 for core 0.
Press 'Q' to Quit.
  2. On another terminal or command prompt, start the GDB and connect to port 54321. For the rest of the walkthrough, this terminal is called as GBD.
    $ riscv32-unknown-elf-gdb.exe app_hal.elf

GNU gdb (GDB) 12.1
Copyright (C) 2022 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
    <http://www.gnu.org/software/gdb/documentation/>.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from app_hal.elf...

(gdb) target remote:54321
Remote debugging using :54321
0x00000008 in ?? ()
    Upon success, the Ashling* GDBServer responds with the following messages. 
    Got a debugger connection from 127.0.0.1 on port 54321.
  3. You can start debugging the Nios® V processor application ELF in the GDB with GDB connected to the Ashling* GDBServer.
    (gdb) load
Loading section .entry, size 0x20 lma 0x0
Loading section .exceptions, size 0x29c lma 0x20
Loading section .text, size 0x18bf4 lma 0x2bc
Loading section .rodata, size 0xf70 lma 0x18eb0
Loading section .rwdata, size 0x1bd8 lma 0x1b9f8
Start address 0x00000354, load size 113144
Transfer rate: 6 KB/sec, 927 bytes/write.

(gdb) b main
Breakpoint 1 at 0x324: file sw/app_hal/hello.c, line 16
(gdb) continue
Continuing.
Breakpoint 1, main () at sw/app_hal/hello.c:16
  4. To quit the GDB, use the exit command, and answer y to detach from the processor.
    (gdb) exit
A debugging session is active.

        Inferior 1 [Remote target] will be detached.

Quit anyway? (y or n) y
Detaching from program: app_hal.elf, Remote target
Ending remote debugging.
[Inferior 1 (Remote target) detached]
  5. Upon quitting GDB, the Ashling* GDBServer responds with the following messages. Continue to quit the Ashling* GDBServer by pressing Q.
    Debugger disconnected, closed connection to 127.0.0.1 on port 54321.
Q
Quitting...
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