Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

6.4. ARM HPS Core Example

The following example shows how to run Ashling* GDBServer at port 12345 on Agilex™ 7 FPGA F-Series Transceiver-SOC Development Kit (Production 1 P-Tiles and E-Tiles) GHRD (DK-SI-AGF014EA) with Ashling Sample Project.
  1. Locate the Ashling Sample Project for Agilex™ 7 SoC Development Kit in <Intel Quartus Prime installation directory>/riscfree/examples/agilex/agilex-a53-sum.zip.
    $ jtagconfig.exe -d
1) Agilex SI/SoC Dev Kit on 10.107.209.0:3560 [3-1.4.1]
   (JTAG Server Version 22.1.0 Build 174 03/30/2022 SC Pro Edition)
  6BA00477   S10HPS/AGILEX_HPS/N5X_HPS (IR=4)
  C341A0DD   AGFB014R24A(.|R1|R2)/.. (IR=10)
  031830DD   10M16S(A|C|L) (IR=10)

  Captured DR after reset = (6BA00477C341A0DD031830DD) [96]
  Captured IR after reset = (100555) [24]
  Captured Bypass after reset = (0) [3]
  Captured Bypass chain = (0) [3]
  JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0
  JTAG clock speed 24 MHz
  2. On the first terminal or command prompt, start the Ashling* GDBServer. For the rest of the walkthrough, this terminal is called as Ashling* GDBServer.
    $ ash-arm-gdb-server.exe --device 6BA00477 \
--auto-detect true --probe-type usb-blaster-2 \
--core-number 0 --jtag-frequency auto-adjust \
--gdb-port 12345

Ashling GDB Server for ARM (ash-arm-gdb-server).
v23.3.2, 01-Sep-2023, (c)Ashling Microsystems Ltd 2023.

Checking for an active debug connection using the selected debug probe (SN: 16777217):
Connected to target device with IDCODE 0x6ba00477 using USB-Blaster-2 via JTAG at adaptive speed.
Waiting for debugger connection on port 12345 for core 0.
Press 'Q' to Quit.
  3. On another terminal or command prompt, start the GDB and connect to port 12345. For the rest of the walkthrough, this second terminal is called as GDB.
    $ aarch64-none-elf-gdb.exe agilex-a53-sum.elf 

GNU gdb (GDB) 13.1
Copyright (C) 2023 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=aarch64-none-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
    <http://www.gnu.org/software/gdb/documentation/>.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from agilex-a53-sum.elf...

(gdb) target remote:12345
Remote debugging using :12345
0x00000000ffe00000 in ?? ()

    Upon success, the Ashling* GDBServer responds with the following messages. 

    Got a debugger connection from 127.0.0.1 on port 12345.
  4. With GDB connected to the Ashling* GDBServer, you can start debugging the Arm* HPS core application ELF in the GDB.
    (gdb) load
Loading section .text, size 0x718 lma 0x7fe00300
Loading section .init, size 0x34 lma 0x7fe00a18
Loading section .fini, size 0x34 lma 0x7fe00a4c
Loading section .rodata, size 0x58 lma 0x7fe00a80
Loading section .eh_frame, size 0x4 lma 0x7fe00ad8
Loading section .data, size 0x758 lma 0x7fe00ae0
Loading section .init_array, size 0x8 lma 0x7fe01238
Loading section .fini_array, size 0x8 lma 0x7fe01240
Start address 0x000000007fe00468, load size 3908
Transfer rate: 592 bytes/sec, 488 bytes/write.

(gdb) b main
Breakpoint 1 at 0x7fe004ec: file ../main.c, line 32. 
(gdb) continue
Continuing.

Breakpoint 1, main () at ../main.c:32
  5. To quit the GDB, use the exit command, and answer y to detach from the processor.
    (gdb) exit
A debugging session is active.

        Inferior 1 [Remote target] will be detached.

Quit anyway? (y or n) y
Detaching from program: agilex-a53-sum.elf, Remote target
Ending remote debugging.
[Inferior 1 (Remote target) detached]
  6. Upon quitting GDB, the Ashling* GDBServer responds with the following messages. Continue to quit the Ashling* GDBServer by pressing Q.
    Debugger disconnected, closed connection to 127.0.0.1 on port 12345.
Q
Quitting...
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