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1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
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3.1.2. Ethernet Multirate Hardware Design Example
Figure 11. Ethernet Multirate Hardware Design Example Block Diagram for 25GE-1 Base Variant
Figure 12. Ethernet Multirate Hardware Design Example Block Diagram for 100GE-4 Base Variant
In the hardware design example, the reset, status, and control signals from packet clients, F-Tile Ethernet Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.
Hardware Flow for Design Example:
The hardware test design contains a hwtest subdirectory that contains .tcl scripts for dynamic reconfiguration.
- Open System Console and navigate to the hwtest directory.
cd hwtest
- Run the script. The script performs the dynamic reconfiguration steps and starts the packet client interface for the different datarates.
source main_script.tcl