F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench Simulation Flow: Dynamic Reconfiguration Sequence Example: 53.1G > 25.7G > 53.1G FEC > 24.3G > 10.1G > 9.8G > 53.1G
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench

The PMA/FEC Direct PHY Multirate design example supports the configurations shown in the following table.
Table 11.  PMA/FEC Direct PHY Multirate Design Example Configurations
Base Variant Variants Available for Dynamic Reconfiguration
50G-1 53.1250Gbps (PAM4) PMA Direct
53.1250Gbps (PAM4) FEC Direct (544,514)
25.7812Gbps (NRZ) PMA Direct
24.3302Gbps (NRZ) PMA Direct
10.3125Gbps (NRZ) PMA Direct
10.1376Gbps (NRZ) PMA Direct
9.8304Gbps (NRZ) PMA Direct
4.9152Gbps (NRZ) PMA Direct
2.4576Gbps (NRZ) PMA Direct
The PMA/FEC Direct PHY Multirate example design simulation testbench block diagram is shown in the following figure.
Figure 13. Simulation Testbench Block Diagram for 50G-1 Base Variant

The testbench program controls the testbench components via Avalon® memory-mapped interface access, status and control signals. The Avalon® memory-mapped interface arbiter decodes the Avalon® memory-mapped interface access from the testbench program into multiple Avalon® memory-mapped interface slaves.

The testwrap block internally consists of the PRBS generator and PRBS verifier. There are 2 types of testwrap blocks:
  • PMA testwrap – used in PMA direct configurations.
  • FEC testwrap – used in FEC direct configuration.
For datarates 25.7812Gbps and below in the 50G-1 base variant, the design shares a single 25G PMA testwrap.

There are two reference clocks being fed into the F-Tile Reference and System PLL Clocks Intel FPGA IP of the 50G-1 base variant. Reference clock of 156.25 MHz is used for Ethernet protocol datarates, while the reference clock of 122.88 MHz is used for CPRI protocol datarates.

Simulation Flow:

  • The PMA/FEC Direct PHY Multirate IP is power-up based on base profile.
  • Initialize the testbench variables based on power-up profile. The parameter settings, located in the top_tst.sv file, are:
    • DR_NUM: To indicate the number of dynamic reconfiguration transitions.
    • DR_SEQ: To indicate the dynamic reconfiguration sequence.
  • Perform dynamic reconfiguration based on the sequence in the parameter settings.
  • Check the testbench error flag and determine whether testbench passed or failed. The error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.

For customization, you can modify the DR_NUM and DR_SEQ localparam, located in the top_tst.sv file to configure the test flow. The profile ID is passed to the IP to configure the intended dynamic reconfiguration task.

Dynamic Reconfiguration Sequence Example: 53.1G > 25.7G > 53.1G FEC > 24.3G > 10.1G > 9.8G > 53.1G

To achieve this dynamic reconfiguration sequence, you must perform six dynamic reconfiguration transitions and specify the reconfiguration sequence. You update the local parameter settings file as follows: 
// Available Modes
localparam DR_MODE_50G_1      = 4'b0000; // ETH
localparam DR_MODE_25G_1      = 4'b0001; // ETH
localparam DR_MODE_24G_1      = 4'b0010; // CPRI
localparam DR_MODE_10p1G_1    = 4'b0011; // CPRI
localparam DR_MODE_9p8G_1     = 4'b0100; // CPRI
localparam DR_MODE_4p9G_1     = 4'b0101; // CPRI
localparam DR_MODE_2p4G_1     = 4'b0110; // CPRI
localparam DR_MODE_10G_1      = 4'b0111; // ETH
localparam DR_MODE_50GKP_1    = 4'b1000; // ETH

// DR from base variant (DR_MODE_50G_1) to other variants in the following order, starting from left.
localparam DR_NUM = 6;
localparam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_25G_1,DR_MODE_50GKP_1,DR_MODE_24G_1,DR_MODE_10p1G_1,DR_MODE_9p8G_1,DR_MODE_50G_1};
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