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1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
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4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
Address Range (Word Addressing) | Maps to |
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0x00000000 - 0x00007FFF | PMA/FEC Direct PHY Soft CSR Avalon® Memory-Mapped Registers.
Note: For PMA/FEC Direct PHY Soft CSR registers and Reconfiguration Soft CSR registers, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map. The register addresses in the reference document use byte addressing format instead of word addressing format.
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0x10000000 - 0x100003FF | Dynamic Reconfiguration Controller Registers.
Note: For a complete list and detailed information about the Dynamic Reconfiguration control and status registers, refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide; Configuration Registers.
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