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1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
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1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters
Figure 5. PMA/FEC Direct PHY Multirate Example Design Tab
Parameters | Value | Description |
---|---|---|
Select Protocol | PMA/FEC Direct PHY |
Select the IP protocol for dynamic reconfiguration. |
Select Base Variant | 50G-1 |
Select the configuration of base variant for dynamic reconfiguration. |
Example Design Files | Simulation | Simulation option generates the testbench and compilation-only project.
Note: Hardware design example support will be available in a future version of the Intel® Quartus® Prime Pro Edition.
|
Generated File Format | Verilog | Select the HDL files format. |
Target Development Kit | None | Target development kit option specifies the target device used to generate the project. |