F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.03.28 22.1
  • Updated the Supported Configuration table in Quick Start Guide:
    • Added new target variants for the Ethernet 100GE-1 base variant
    • Added 400GE-8 base variant for Ethernet IP protocol
    • Added 50G-1 base variant for PMA/FEC direct IP protocol
  • Removed support for the ModelSim* SE simulator.
  • Updated Ethernet Multirate Design Example Parameters to include 400G-8 base variant and the dev kit support.
  • Updated steps in section: Simulating the Design Example Testbench.
  • Updated Directory Structure:
    • Added PMA/FEC Direct PHY-specific testbench files
    • Added Ethernet-specific hardware design example files
  • Added new figure: Simulation Testbench Block Diagram for 400GE-8 Base Variant
  • Added hardware support for the Ethernet Multirate Design Example.
  • Added support for PMA/FEC Direct PHY Multirate design example.
2022.01.07 21.4
  • Added support for Ethernet Multirate design example.
  • Added support for the Xcelium* simulator.
  • Added hardware support for the CPRI Multirate Design Example.
  • Updated the Simulation Testbench Block Diagram and the customization instructions in section: CPRI Multirate Design Example: Simulation Testbench.
  • Updated the address range in section: CPRI Multirate Design Example: Registers.
2021.11.17 21.3 Initial release.
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