AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

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ID 709330
Date 3/27/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.3. System Description

The following system-level diagram shows how the different modules are connected in this design.

Figure 3. System Diagram

In this setup, for example L = 6, M = 12, and F = 4, the data rate of transceiver lanes is 24.75 Gbps.

The Si5341 OUT4 generates 100 MHz clock to mgmt_clk. The E-tile transceiver reference clock is subjected to multiplexing and is done with 3 clock sources. The first clock is the refclk_xcvr signal, which is supplied from the FPGA onboard oscillator and has the frequency of 156.25 MHz. The second clock is the refclk_xcvr1 signal, which is supplied from Si5341 OUT1 clock generator and has the frequency of 156.25 MHz.

The Si5341 out4 generates 100 MHz clock to mgmt_clk. The E-tile transceiver has 3 clock sources—LMK onboard oscillator (156.25 MHz), Si5341 OUT0 (156.25 MHz), and HMC7044 OUT8. The HMC7044 generates the transceiver reference clock frequency of 375 MHz. This clock is refclk_xcvr4, which is Lane Rate*1000/66 in its frequency. Refer to the Clock Multiplexing section for the need and procedure for switching clocks.

The HMC7044 also generates 187.5 MHz for the JESD204C Intel® FPGA IP's core PLL reference clock and a periodic SYSREF signal of 11.71875 MHz through the FMC connector.

The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the receiver path is used. For FCLK_MULP =1, WIDTH_MULP = 4, and S = 1, the core PLL generates a 187.5 MHz link clock and a 187.5 MHz frame clock. The rx_dl_signal signal is for deterministic latency measurement.

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