AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

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ID 709330
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.2.1. Switching Reference Clocks

The E-tile transceiver has two fixed clock source (oscillator and Si5341) and one programmable clock source from the HMC7044 chip. To work with different lane rates programmable clock source is necessary.

The HMC7044 chip is in the AD9081 EVM and has an SPI interface to configure it. This SPI interface is controlled by the Intel Agilex® 7 FPGA. The E-tile transceiver requires a free running clock when the FPGA is configured after powered on. During initial power on configuration, the fixed clock source is used and then switched to the HMC7044 clock output, once the HMC chip is configured.

Intel recommends the source synchronous clocks for transceiver reference clock and the JESD204C dual IP IOPLL input clock. The HMC7044 chip provides flexibility to reconfigure for different lane rate. For this purpose, clock outputs from the HMC7044 chip are utilized.


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Procedure

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