AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

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ID 709330
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.5. JESD204C Intel® FPGA IP and ADC Configurations

The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device. The transceiver data rate, sampling clock, and other JESD204C parameters comply with the AD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configuration in the table below.

Global setting for all configuration:
  • CF = 0
  • CS = 0
  • Subclass = 1
  • SH_CONFIG = CRC-12
  • FPGA Management Clock (MHz) = 100
Note: The other configurations are retained at default values.
Table 5.  Parameter Configuration
No. L M F S HD E N NP ADC Sampling Clock (MHz) FPGA Device Clock (MHz) Coarse Decimation Fine Decimation Lane Rate (Gbps) Data Pattern
1 1 2 4 1 0 1 16 16 1966.08 245.76 2 2 16.22016 PRBS15 Ramp
2 1 2 3 1 0 3 12 12 2211.84 276.48 1 3 18.24768 PRBS15 Ramp
3 1 4 6 1 0 3 12 12 2949.12 184.32 3 4 12.16512 PRBS15 Ramp
4 1 4 8 1 0 1 16 16 3000 375 4 2 24.75 PRBS15 Ramp
5 1 8 12 1 0 3 12 12 1474.56 184.32 2 6 12.16512 PRBS15 Ramp
6 1 8 16 1 0 2 16 16 2621.44 327.68 8 2 21.62688 PRBS15 Ramp
7 1 8 24 1 0 3 16 24 1966.08 184.32 8 4 12.16512 PRBS15 Ramp
8 2 2 2 1 0 1 16 16 1500 375 1 1 24.75 PRBS15 Ramp
9 2 2 3 2 0 3 12 12 2621.44 245.76 1 2 16.22016 PRBS15 Ramp
10 2 4 3 1 0 3 12 12 2949.12 184.32 2 3 12.16512 PRBS15 Ramp
11 2 4 4 1 0 1 16 16 1474.56 184.32 2 2 12.16512 PRBS15 Ramp
12 2 8 6 1 0 3 12 12 3000 375 1 6 24.75 PRBS15 Ramp
13 2 8 8 1 0 1 16 16 1474.56 184.32 4 2 12.16512 PRBS15 Ramp
14 2 8 12 1 0 3 16 24 1474.56 184.32 3 4 12.16512 PRBS15 Ramp
15 3 6 4 1 0 1 16 16 1474.56 184.32 2 2 12.16512 PRBS15 Ramp
16 3 12 8 1 0 1 16 16 2949.12 245.76 3 4 16.22016 PRBS15 Ramp
17 4 2 1 1 1 1 16 16 1474.56 184.32 1 1 12.16512 PRBS15 Ramp
18 4 2 3 4 0 3 12 12 3440.64 322.56 1 1 21.28896 PRBS15 Ramp
19 4 4 2 1 0 1 16 16 1500 375 1 1 24.75 PRBS15 Ramp
20 4 4 3 2 0 3 12 12 2621.44 245.76 1 2 16.22016 PRBS15 Ramp
21 4 8 3 1 0 3 12 12 1474.56 276.48 1 2 18.24768 PRBS15 Ramp
22 4 8 4 1 0 1 16 16 1474.56 184.32 2 2 12.16512 PRBS15 Ramp
23 4 8 6 1 0 3 16 24 3440.64 322.56 2 4 21.28896 PRBS15 Ramp
24 4 16 8 1 0 1 16 16 1474.56 184.32 4 2 12.16512 PRBS15 Ramp
25 6 12 4 1 0 1 16 16 3000 375 2 2 24.75 PRBS15 Ramp
26 8 2 1 2 1 1 16 16 2949.12 184.32 1 1 12.16512 PRBS15 Ramp
27 8 2 3 8 0 3 12 12 3932.16 184.32 1 1 12.16512 PRBS15 Ramp
28 8 4 1 1 0 3 16 16 3000 375 1 1 24.75 PRBS15 Ramp
29 8 4 3 4 0 3 12 12 1966.08 184.32 1 1 12.16512 PRBS15 Ramp
30 8 8 2 1 0 1 16 16 1474.56 184.32 1 2 12.16512 PRBS15 Ramp
31 8 8 3 2 0 3 12 12 3932.16 245.76 1 3 16.22016 PRBS15 Ramp
32 8 8 3 1 0 3 16 24 2211.84 276.48 1 3 18.24768 PRBS15 Ramp
33 8 16 8 2 0 1 16 16 2211.84 184.32 3 2 12.16512 PRBS15 Ramp
34 2 4 4 1 0 1 16 16 1966.08 245.76 4 2 8.11008 PRBS15 Ramp
35 4 2 1 2 1 1 16 16 3932.16 245.76 4 1 8.11008 PRBS15 Ramp
Level Two Title